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| Datasheet File OCR Text: |
| this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. september 2013 doc id 16315 rev 7 1/90 1 spc560d30x spc560d40x 32-bit mcu family built on the power architecture ? for automotive body electronics applications datasheet ? preliminary data features high-performance up to 48 mhz e200z0h cpu ? 32-bit power architecture ? technology cpu ? variable length encoding (vle) memory ? up to 256 kb code flash with ecc ? up to 64 (4x16) kb data flash with ecc ? up to 16 kb sram with ecc interrupts ? 16 priority levels ? non-maskable interrupt (nmi) ? up to 38 external interrupts incl. 18 wakeup lines 16-channel edma gpios: 45 (lqfp64), 79 (lqfp100) timer units ? 4-channel 32-bit periodic interrupt timers ? 4-channel 32-bit system timer module ? system watchdog timer ? 32 bit real-time clock timer 16-bit counter time-triggered i/os ? up to 28 channels with pwm/mc/ic/oc ? 5 independent counters ? 27 ch. with adc trigger capability 12-bit analog-to-digital converter (adc) with up to 33 channels ? up to 61 channels via external multiplexing ? individual conversion registers ? cross triggering unit (ctu) dedicated diagnostic module for lighting ? advanced pwm generation ? time-triggered diagnostics ? pwm-synchronized adc measurements communications interfaces ? 1 flexcan interface (2.0b active) with 32 message buffers ? 3 linflex/uart, 1 with dma capability ?2 dspi clock generation ? 4 to 16 mhz fast external crystal oscillator ? 16 mhz fast internal rc oscillator ? 128 khz slow internal rc oscillator ? software-controlled fmpll ? clock monitoring unit exhaustive debugging capability ? nexus1 on all packages ? nexus2+ available on emulation device (spc560b64b2-eng) on-chip can/uart bootstrap loader low power capabilities ? several low power mode configurations ? ultra-low power standby with rtc,sram and can monitoring ? fast wakeup schemes single 5 v or 3.3 v supply operates in ambient temperature range of -40 to 125 c table 1. device summary package part number 128 kbyte code flash 256 kbyte code flash lqfp100 spc560d30l3 spc560d40l3 lqfp64 spc560d30l1 spc560d40l1 lqfp100 (14 x 14 x 1.4 mm) lqfp64 (10 x 10 x 1.4 mm) www.st.com
contents spc560d30x, spc56040dx 2/90 doc id 16315 rev 7 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 package pinouts and signal descr iptions . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 pad configuration during reset phases . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 voltage supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5 system pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.6 functional ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.2 parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3 nvusro register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.3.1 nvusro[pad3v5v] field description . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.3.2 nvusro[oscillator_margin] field description . . . . . . . . . . . . . . . 29 4.3.3 nvusro[watchdog_en] field description . . . . . . . . . . . . . . . . . . . . 29 4.4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.5 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.6 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.6.1 package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.6.2 power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.7 i/o pad electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.7.1 i/o pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.7.2 i/o input dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.7.3 i/o output dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.7.4 output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.7.5 i/o pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.8 reset electrical characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 spc560d30x, spc56040dx contents doc id 16315 rev 7 3/90 4.9 power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 44 4.9.1 voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 44 4.9.2 low voltage detector electrical characteristics . . . . . . . . . . . . . . . . . . . . 47 4.10 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.11 flash memory electrical char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.11.1 program/erase characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.11.2 flash power supply dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.11.3 start-up/switch-off timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.12 electromagnetic compatibility (emc) charac teristics . . . . . . . . . . . . . . . . 52 4.12.1 designing hardened software to avoid noise problems . . . . . . . . . . . . . 52 4.12.2 electromagnetic interference (emi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.12.3 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 53 4.13 fast external crystal oscillator (4 to 16 mhz) electrical characteristics . . 55 4.14 fmpll electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.15 fast internal rc oscillator (16 mhz) el ectrical characteristics . . . . . . . . . 58 4.16 slow internal rc oscillator (128 khz) electrical characteristics . . . . . . . . 59 4.17 adc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.17.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.17.2 input impedance and adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.17.3 adc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.18 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.18.1 current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.18.2 dspi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.18.3 jtag characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.1 ecopack? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.2 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.2.1 lqfp100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.2.2 lqfp64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 appendix a abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 list of tables spc560d30x, spc56040dx 4/90 doc id 16315 rev 7 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. spc560d30, spc560d40 device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. spc560d30, spc560d40 series block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. voltage supply pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 5. system pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 6. functional port pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 7. parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 8. pad3v5v field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 9. oscillator_margin field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 10. watchdog_en field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 11. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 12. recommended operating conditions (3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 13. recommended operating conditions (5.0 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 14. lqfp thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 15. i/o input dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 16. i/o pull-up/pull-down dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 17. slow configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 36 table 18. medium configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 37 table 19. output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 20. i/o supply segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 21. i/o consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 22. i/o weight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 23. reset electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 24. voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 25. low voltage detector electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 26. power consumption on vdd_bv and vdd_hv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 27. program and erase specifications (code flash). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 28. program and erase specifications (data flash) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 29. flash module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 30. flash memory read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 31. flash power supply dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 32. start-up time/switch-off time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 33. emi radiated emission measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 34. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 35. latch-up results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 36. crystal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 37. fast external crystal oscillator (4 to 16 mhz) electrical characteristics. . . . . . . . . . . . . . . . 56 table 38. fmpll electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 39. fast internal rc oscillator (16 mhz) electrical ch aracteristics . . . . . . . . . . . . . . . . . . . . . . 58 table 40. slow internal rc oscillator (128 khz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . 59 table 41. adc input leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 42. adc conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 43. on-chip peripherals current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 44. dspi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 45. jtag characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 46. lqfp100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 47. lqfp64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 48. order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 spc560d30x, spc56040dx list of tables doc id 16315 rev 7 5/90 table 49. order codes for engineering samples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 table 50. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 list of figures spc560d30x, spc56040dx 6/90 doc id 16315 rev 7 list of figures figure 1. spc560d30, spc560d40 series block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2. lqfp100 pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 figure 3. lqfp64 pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4. input dc electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 5. start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 6. noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 7. voltage regulator capacitance connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 8. low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 9. crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 10. fast external crystal oscillato r (4 to 16 mhz) timing diagram . . . . . . . . . . . . . . . . . . . . . . . 56 figure 11. adc characteristics and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 12. input equivalent circuit (precise channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 13. input equivalent circuit (extended channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 14. transient behavior during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 15. spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 16. dspi classic spi timing ? master, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 17. dspi classic spi timing ? master, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 18. dspi classic spi timing ? slave, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 19. dspi classic spi timing ? slave, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 20. dspi modified transfer format timing ? master, cpha = 0. . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 21. dspi modified transfer format timing ? master, cpha = 1. . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 22. dspi modified transfer format timing ? slave, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 23. dspi modified transfer format timing ? slave, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 24. dspi pcs strobe (pcss) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 25. timing diagram ? jtag boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 26. lqfp100 mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 27. lqfp64 mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 28. commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 spc560d30x, spc56040dx introduction doc id 16315 rev 7 7/90 1 introduction 1.1 document overview this document describes the device features and highlights the important electrical and physical characteristics. 1.2 description these 32-bit automotive microcontrollers ar e a family of system-on-chip (soc) devices designed to be central to the development of the next wave of central vehicle body controller, smart junction box, front module, peripheral body, door control and seat control applications. this family is one of a series of next-generation integrated automotive microcontrollers based on the power architecture technology and designed specifically for embedded applications. the advanced and cost-efficient e200z0h host processor core of this automotive controller family complies with the power architecture technology and only implements the vle (variable-length encoding) apu (a uxiliary processing unit), prov iding improved code density. it operates at speeds of up to 48 mhz and offers high performance processing optimized for low power consumption. it capitalizes on the available development infrastructure of current power architecture devices and is supported with software drivers, operating systems and configuration code to assist with the user?s implementations. the device platform has a single level of memory hierarchy and can support a wide range of on-chip static random access memory (sram) and internal flash memory. table 2. pictus 512k device comparison feature device spc560d30l1 spc560d30l3 spc560d40l1 spc560d40l3 cpu e200z0h execution speed static ? up to 48 mhz code flash memory 128 kb 256 kb data flash memory 64 kb (4 16 kb) sram 12 kb 16 kb edma 16 ch adc (12-bit) 16 ch 33 ch 16 ch 33 ch ctu 16 ch total timer i/o (1) emios 14 ch, 16-bit 28 ch, 16-bit 14 ch, 16-bit 28 ch, 16-bit ? type x (2) 2ch 5ch 2ch 5ch ? type y (3) ?9ch?9ch ? type g (4) 7ch 7ch 7ch 7ch introduction spc560d30x, spc56040dx 8/90 doc id 16315 rev 7 ? type h (5) 4ch 7ch 4ch 7ch sci (linflex) 3 spi (dspi) 2 can (flexcan) 1 gpio (6) 45 79 45 79 debug jtag package lqfp64 lqfp100 lqfp64 lqfp100 1. refer to emios chapter of device reference manual for information on t he channel configurat ion and functions. 2. type x = mc + mcb + opwmt + opwmb + opwfmb + saic + saoc 3. type y = opwmt + opwmb + saic + saoc 4. type g = mcb + ipwm + ipm + daoc + opwmt + opwmb + opwfmb + opwmcb + saic + saoc 5. type h = ipwm + ipm + daoc + opwmt + opwmb + saic + saoc 6. i/o count based on multip lexing with peripherals table 2. pictus 512k device comparison (continued) feature device spc560d30l1 spc560d30l3 spc560d40l1 spc560d40l3 spc560d30x, spc56040dx block diagram doc id 16315 rev 7 9/90 2 block diagram figure 1 shows a top-level block diagram of the pictus 512k device series. figure 1. pictus 512k series block diagram 2 x dspi fmpll nexus 1 sram siul reset control 16 kb external imux gpio & jtag pad control jtag port e200z0h interrupt requests 64-bit 3 x 3 crossbar switch 1 x flexcan peripheral bridge interrupt request interrupt request i/o clocks instructions data voltage regulator nmi swt pit stm nmi siul . . . . . . . . . . . . intc 3 x linflex 1 x emios 33 ch. adc cmu sram flash code flash 256 kb data flash 64 kb mc_pcu mc_me mc_cgm mc_rgm bam ctu rtc sscm (master) (master) (slave) (slave) (slave) controller controller legend: adc analog-to-digital converter bam boot assist module cmu clock monitor unit ctu cross triggering unit dspi deserial serial peripheral interface ecsm error correction status module edma enhanced direct memory access emios enhanced modular input output system flash flash memory flexcan controller area network (flexcan) fmpll frequency-modulated phase-locked loop imux internal multiplexer intc interrupt controller jtag jtag controller linflex serial communication interface (lin support) mc_cgm clock generation module mc_me mode entry module mc_pcu power control unit mc_rgm reset generation module nmi non-maskable interrupt pit periodic interrupt timer rtc real-time clock siul system integration unit lite sram static random-access memory sscm system status configuration module stm system timer module swt software watchdog timer wkpu wakeup unit xbar crossbar switch edma ecsm from peripheral blocks wkpu request interrupt request (master) block diagram spc560d30x, spc56040dx 10/90 doc id 16315 rev 7 ta bl e 3 summarizes the functions of all blocks present in the pictus 512k series of microcontrollers. please note that the presence and number of blocks varies by device and package. table 3. pictus 512k series block summary block function analog-to-digital converter (adc) multi-channel, 12-bit analog-to-digital converter boot assist module (bam) a block of read-only memory containing vle code which is executed according to the boot mode of the device clock generation module (mc_cgm) provides logic and control required for the generation of system and peripheral clocks clock monitor unit (cmu) monitors clock source (internal and external) integrity cross triggering unit (ctu) enables synchronization of adc conversi ons with a timer event from the emios or from the pit crossbar switch (xbar) supports simultaneous connections between two master ports and three slave ports. the crossbar supports a 32-bit address bus width and a 64-bit data bus width. deserial serial peripheral interface (dspi) provides a synchronous serial interface for communication with external devices enhanced direct memory access (edma) performs complex data transfers with minimal intervention from a host processor via ? n ? programmable channels. enhanced modular input output system (emios) provides the functionality to generate or measure events error correction status module (ecsm) provides a myriad of miscellaneous cont rol functions for the device including program-visible information about configuration and revision levels, a reset status register, wakeup control for exiting sleep modes, and optional features such as information on memory erro rs reported by error-correcting codes flash memory provides non-volatile storage for program code, constants and variables flexcan (controller area network) supports the standard can communications protocol frequency-modulated phase- locked loop (fmpll) generates high-speed system clocks and supports programmable frequency modulation internal multiplexer (imux) siu subblock allows flexible mapping of peripheral inte rface on the different pins of the device interrupt controller (intc) provides priority-bas ed preemptive scheduling of interrupt requests jtag controller (jtagc) provides the means to test chip functi onality and connectivity while remaining transparent to system logic when not in test mode linflex controller manages a high number of lin (local interconnect network protocol) messages efficiently with a minimum of cpu load mode entry module (mc_me) provides a mechanism for controlling the device operational mode and mode transition sequences in all functional states; also manage s the power control unit, reset generation module and clock generation module, and holds the configuration, control and status registers accessible for applications non-maskable interrupt (nmi) handles external events that must produce an immediate response, such as power down detection spc560d30x, spc56040dx block diagram doc id 16315 rev 7 11/90 periodic interrupt timer (pit) produces periodic interrupts and triggers power control unit (mc_pcu) reduces the overall power consumption by disconnecting parts of the device from the power supply via a power switching device; device components are grouped into sections called ?power domains? which are controlled by the pcu real-time counter (rtc) provides a free-running counter and interrupt generation capability that can be used for timekeeping applications reset generation module (mc_rgm) centralizes reset sources and manages the device reset sequence of the device static random-access memory (sram) provides storage for program code, constants, and variables system integration unit lite (siul) provides control over all the electrical pad controls and up 32 ports with 16 bits of bidirectional, general-purpose input and output signals and supports up to 32 external interrupts with trigger event configuration system status and configuration module (sscm) provides system configuration and status data (such as memory size and status, device mode and security status ), device identification data, debug status port enable and selection, and bus and peripheral abort enable/disable system timer module (stm) provides a set of output compare events to support autosar (automotive open system architecture) and operating system tasks software watchdog timer (swt) provides protection from runaway code wakeup unit (wkpu) supports up to 18 external sources that can generate interrupts or wakeup events, of which 1 can cause non-maskable interrupt requests or wakeup events. table 3. pictus 512k series block summary (continued) block function package pinouts and signal descriptions spc560d30x, spc56040dx 12/90 doc id 16315 rev 7 3 package pinouts and signal descriptions 3.1 package pinouts the available lqfp pinouts are provided in the following figures. for pin signal descriptions, please refer to ta b l e 6 . spc560d30x, spc56040dx package pi nouts and signal descriptions doc id 16315 rev 7 13/90 figure 2 shows the pictus 512k in the lqfp100 package. figure 2. lqfp100 pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 pb[3] pc[9] pc[14] pc[15] pa [ 2 ] pe[0] pa [ 1 ] pe[1] pe[8] pe[9] pe[10] pa [ 0 ] pe[11] vss_hv vdd_hv vss_hv reset vss_lv vdd_lv vdd_bv pc[11] pc[10] pb[0] pb[1] pc[6] pa[11] pa[10] pa [ 9 ] pa [ 8 ] pa [ 7 ] vdd_hv vss_hv pa [ 3 ] pb[15] pd[15] pb[14] pd[14] pb[13] pd[13] pb[12] pd[12] pb[11] pd[11] pd[10] pd[9] pb[7] pb[6] pb[5] vdd_hv_adc vss_hv_adc pc[7] pa[15] pa[14] pa [ 4 ] pa[13] pa[12] vdd_lv vss_lv xtal vss_hv extal vdd_hv pb[9] pb[8] pb[10] pd[0] pd[1] pd[2] pd[3] pd[4] pd[5] pd[6] pd[7] pd[8] pb[4] pb[2] pc[8] pc[13] pc[12] pe[7] pe[6] pe[5] pe[4] pc[4] pc[5] pe[3] pe[2] ph[9] pc[0] vss_lv vdd_lv vdd_hv vss_hv pc[1] ph[10] pa [ 6 ] pa [ 5 ] pc[2] pc[3] pe[12] lqfp100 package pinouts and signal descriptions spc560d30x, spc56040dx 14/90 doc id 16315 rev 7 figure 3 shows the pictus 512k in the lqfp64 package. figure 3. lqfp64 pin configuration (top view) 3.2 pad configuration during reset phases all pads have a fixed configuration under reset. during the power-up phase, all pads are forced to tristate. after power-up phase, all pads are forced to tristate with the following exceptions: pa[9] (fab) is pull-down. without external strong pull-up the device starts fetching from flash. pa[8] (abs[0]) is pull-up. reset pad is driven low. this is pull- up only after phase2 reset completion. jtag pads (tck, tms and tdi) are pull-up while tdo remains tristate. precise adc pads (pb[7:4] and pd[11:0]) are left tristate (no output buffer available). main oscillator pads (ext al, xtal) are tristate. 3.3 voltage supply pins voltage supply pins are used to provide powe r to the device. two dedicated pins are used for 1.2 v regulator stabilization. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 pb[3] pc[9] pa [ 2 ] pa [ 1 ] pa [ 0 ] vss_hv vdd_hv vss_hv reset vss_lv vdd_lv vdd_bv pc[10] pb[0] pb[1] pc[6] pa [ 1 1 ] pa [ 1 0 ] pa [ 9 ] pa [ 8 ] pa [ 7 ] pa [ 3 ] pb[15] pb[14] pb[13] pb[12] pb[11] pb[7] pb[6] pb[5] vdd_hv_adc vss_hv_adc pc[7] pa[15] pa[14] pa [ 4 ] pa[13] pa[12] vdd_lv vss_lv xtal vss_hv extal vdd_hv pb[9] pb[8] pb[10] pb[4] pb[2] pc[8] pc[4] pc[5] ph[9] pc[0] vss_lv vdd_lv vdd_hv vss_hv pc[1] ph[10] pa [ 6 ] pa [ 5 ] pc[2] pc[3] lqfp64 spc560d30x, spc56040dx package pi nouts and signal descriptions doc id 16315 rev 7 15/90 3.4 pad types in the device the following types of pads are available for system pins and functional port pins: s = slow (a) m = medium (a) (b) f = fast (a) (b) i = input only with analog feature (a) j = input/output (?s? pad) with analog feature x = oscillator 3.5 system pins the system pins are listed in ta b l e 5 . table 4. voltage supply pin descriptions port pin function pin number lqfp64 lqfp100 vdd_hv digital supply voltage 7, 28, 34, 56 15, 37, 52, 70, 84 vss_hv digital ground 6, 8, 26, 33, 55 14, 16, 35, 51, 69, 83 vdd_lv 1.2v decoupling pins. decoupling capacitor must be connected between these pins and the nearest v ss_lv pin. (1) 11, 23, 57 19, 32, 85 vss_lv 1.2v decoupling pins. decoupling capacitor must be connected between these pins and the nearest v dd_lv pin. (1) 10, 24, 58 18, 33, 86 vdd_bv internal regulator supply voltage 12 20 1. a decoupling capacitor must be placed between each of the th ree vdd_lv/vss_lv supply pairs to ensure stable voltage (see the recommended operating conditions in the device datasheet for details). a. see the i/o pad electrical characteri stics in the device datasheet for details. b. all medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium (see the pcr[src] description in the device reference manual). table 5. system pin descriptions port pin function i/o direction pad type reset configuration pin number lqfp64 lqfp100 reset bidirectional reset with schmitt-trigger characteristics and noise filter. i/o m input, weak pull-up only after phase2 917 package pinouts and signal descriptions spc560d30x, spc56040dx 16/90 doc id 16315 rev 7 3.6 functional ports the functional port pins are listed in ta bl e 6 . extal analog output of the oscillator amplifier circuit, when the oscillator is not in bypass mode. analog input for the clock generator when the oscillator is in bypass mode. (1) i/o x tristate 27 36 xtal analog input of the oscillator amplifier circuit. needs to be grounded if oscillator is used in bypass mode. (1) i x tristate 25 34 1. refer to the relevant section of the device datasheet. table 5. system pin descriptions (continued) port pin function i/o direction pad type reset configuration pin number lqfp64 lqfp100 table 6. functional port pin descriptions port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 port a pa[0] pcr[0] af0 af1 af2 af3 ? gpio[0] e0uc[0] clkout e0uc[13] wkpu[19] (3) siul emios_0 cgl emios_0 wkpu i/o i/o o i/o i mtristate 5 12 pa[1] pcr[1] af0 af1 af2 af3 ? ? gpio[1] e0uc[1] ? ? nmi (4) wkpu[2] (3) siul emios_0 ? ? wkpu wkpu i/o i/o ? ? i i s tristate 4 7 pa[2] pcr[2] af0 af1 af2 af3 ? gpio[2] e0uc[2] ? ma[2] wkpu[3] (3) siul emios_0 ? adc wkpu i/o i/o ? o i s tristate 3 5 spc560d30x, spc56040dx package pi nouts and signal descriptions doc id 16315 rev 7 17/90 pa[3] pcr[3] af0 af1 af2 af3 ? ? gpio[3] e0uc[3] ? cs4_0 eirq[0] adc1_s[0] siul emios_0 ? dspi_0 siul adc i/o i/o ? i/o i i s tristate 43 68 pa[4] pcr[4] af0 af1 af2 af3 ? gpio[4] e0uc[4] ? cs0_1 wkpu[9] (3) siul emios_0 ? dspi_1 wkpu i/o i/o ? i/o i s tristate 20 29 pa[5] pcr[5] af0 af1 af2 af3 gpio[5] e0uc[5] ? ? siul emios_0 ? ? i/o i/o ? ? m tristate 51 79 pa[6] pcr[6] af0 af1 af2 af3 ? gpio[6] e0uc[6] ? cs1_1 eirq[1] siul emios_0 ? dspi_1 siul i/o i/o ? i/o i s tristate 52 80 pa[7] pcr[7] af0 af1 af2 af3 ? ? gpio[7] e0uc[7] ? ? eirq[2] adc1_s[1] siul emios_0 ? ? siul adc i/o i/o ? ? i i s tristate 44 71 pa[8] pcr[8] af0 af1 af2 af3 ? n/a (5) gpio[8] e0uc[8] e0uc[14] ? eirq[3] abs[0] siul emios_0 emios_0 ? siul bam i/o i/o ? ? i i s input, weak pull-up 45 72 pa[9] pcr[9] af0 af1 af2 af3 n/a (5) gpio[9] e0uc[9] ? cs2_1 fab siul emios_0 ? dspi_1 bam i/o i/o ? i/o i s pull-down 46 73 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 package pinouts and signal descriptions spc560d30x, spc56040dx 18/90 doc id 16315 rev 7 pa [ 1 0 ] p c r [ 1 0 ] af0 af1 af2 af3 ? gpio[10] e0uc[10] ? lin2tx adc1_s[2] siul emios_0 ? linflex_2 adc i/o i/o ? o i s tristate 47 74 pa [ 1 1 ] p c r [ 1 1 ] af0 af1 af2 af3 ? ? ? gpio[11] e0uc[11] ? ? eirq[16] adc1_s[3] lin2rx siul emios_0 ? ? siul adc linflex_2 i/o i/o ? ? i i i s tristate 48 75 pa [ 1 2 ] p c r [ 1 2 ] af0 af1 af2 af3 ? ? gpio[12] ? ? ? eirq[17] sin_0 siul ? ? ? siul dspi_0 i/o ? ? ? i i s tristate 22 31 pa [ 1 3 ] p c r [ 1 3 ] af0 af1 af2 af3 gpio[13] sout_0 ? cs3_1 siul dspi_0 ? dspi_1 i/o o ? i/o m tristate 21 30 pa [ 1 4 ] p c r [ 1 4 ] af0 af1 af2 af3 ? gpio[14] sck_0 cs0_0 e0uc[0] eirq[4] siul dspi_0 dspi_0 emios_0 siul i/o i/o i/o i/o i m tristate 19 28 pa [ 1 5 ] p c r [ 1 5 ] af0 af1 af2 af3 ? gpio[15] cs0_0 sck_0 e0uc[1] wkpu[10] (3) siul dspi_0 dspi_0 emios_0 wkpu i/o i/o i/o i/o i m tristate 18 27 port b pb[0] pcr[16] af0 af1 af2 af3 gpio[16] can0tx ? lin2tx siul flexcan_0 ? linflex_2 i/o o ? o m tristate 14 23 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 spc560d30x, spc56040dx package pi nouts and signal descriptions doc id 16315 rev 7 19/90 pb[1] pcr[17] af0 af1 af2 af3 ? ? gpio[17] ? ? lin0rx wkpu[4] (3) can0rx siul ? ? linflex_0 wkpu flexcan_0 i/o ? ? i i i s tristate 15 24 pb[2] pcr[18] af0 af1 af2 af3 gpio[18] lin0tx ? ? siul linflex_0 ? ? i/o o ? ? mtristate 64 100 pb[3] pcr[19] af0 af1 af2 af3 ? ? gpio[19] ? ? ? wkpu[11] (3) lin0rx siul ? ? ? wkpu linflex_0 i/o ? ? ? i i s tristate 1 1 pb[4] pcr[20] af0 af1 af2 af3 ? gpio[20] ? ? ? adc1_p[0] siul ? ? ? adc i ? ? ? i i tristate 32 50 pb[5] pcr[21] af0 af1 af2 af3 ? gpio[21] ? ? ? adc1_p[1] siul ? ? ? adc i ? ? ? i i tristate 35 53 pb[6] pcr[22] af0 af1 af2 af3 ? gpio[22] ? ? ? adc1_p[2] siul ? ? ? adc i ? ? ? i i tristate 36 54 pb[7] pcr[23] af0 af1 af2 af3 ? gpio[23] ? ? ? adc1_p[3] siul ? ? ? adc i ? ? ? i i tristate 37 55 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 package pinouts and signal descriptions spc560d30x, spc56040dx 20/90 doc id 16315 rev 7 pb[8] pcr[24] af0 af1 af2 af3 ? ? gpio[24] ? ? ? adc1_s[4] wkpu[25] (3) siul ? ? ? adc wkpu i ? ? ? i i i tristate 30 39 pb[9] pcr[25] af0 af1 af2 af3 ? ? gpio[25] ? ? ? adc1_s[5] wkpu[26] (3) siul ? ? ? adc wkpu i ? ? ? i i i tristate 29 38 pb[10] pcr[26] af0 af1 af2 af3 ? ? gpio[26] ? ? ? adc1_s[6] wkpu[8] (3) siul ? ? ? adc wkpu i/o ? ? ? i i j tristate 31 40 pb[11] pcr[27] af0 af1 af2 af3 ? gpio[27] e0uc[3] ? cs0_0 adc1_s[12] siul emios_0 ? dspi_0 adc i/o i/o ? i/o i j tristate 38 59 pb[12] pcr[28] af0 af1 af2 af3 ? gpio[28] e0uc[4] ? cs1_0 adc1_x[0] siul emios_0 ? dspi_0 adc i/o i/o ? o i j tristate 39 61 pb[13] pcr[29] af0 af1 af2 af3 ? gpio[29] e0uc[5] ? cs2_0 adc1_x[1] siul emios_0 ? dspi_0 adc i/o i/o ? o i j tristate 40 63 pb[14] pcr[30] af0 af1 af2 af3 ? gpio[30] e0uc[6] ? cs3_0 adc1_x[2] siul emios_0 ? dspi_0 adc i/o i/o ? o i j tristate 41 65 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 spc560d30x, spc56040dx package pi nouts and signal descriptions doc id 16315 rev 7 21/90 pb[15] pcr[31] af0 af1 af2 af3 ? gpio[31] e0uc[7] ? cs4_0 adc1_x[3] siul emios_0 ? dspi_0 adc i/o i/o ? o i j tristate 42 67 port c pc[0] (6) pcr[32] af0 af1 af2 af3 gpio[32] ? tdi ? siul ? jtagc ? i/o ? i ? m input, weak pull-up 59 87 pc[1] (6) pcr[33] af0 af1 af2 af3 gpio[33] ? tdo ? siul ? jtagc ? i/o ? o ? f tristate 54 82 pc[2] pcr[34] af0 af1 af2 af3 ? gpio[34] sck_1 ? ? eirq[5] siul dspi_1 ? ? siul i/o i/o ? ? i m tristate 50 78 pc[3] pcr[35] af0 af1 af2 af3 ? gpio[35] cs0_1 ma[0] ? eirq[6] siul dspi_1 adc ? siul i/o i/o o ? i s tristate 49 77 pc[4] pcr[36] af0 af1 af2 af3 ? ? gpio[36] ? ? ? sin_1 eirq[18] siul ? ? ? dspi_1 siul i/o ? ? ? i i m tristate 62 92 pc[5] pcr[37] af0 af1 af2 af3 ? gpio[37] sout_1 ? ? eirq[7] siul dspi_1 ? ? siul i/o o ? ? i m tristate 61 91 pc[6] pcr[38] af0 af1 af2 af3 gpio[38] lin1tx ? ? siul linflex_1 ? ? i/o o ? ? s tristate 16 25 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 package pinouts and signal descriptions spc560d30x, spc56040dx 22/90 doc id 16315 rev 7 pc[7] pcr[39] af0 af1 af2 af3 ? ? gpio[39] ? ? ? lin1rx wkpu[12] (3) siul ? ? ? linflex_1 wkpu i/o ? ? ? i i s tristate 17 26 pc[8] pcr[40] af0 af1 af2 af3 gpio[40] lin2tx e0uc[3] ? siul linflex_2 emios_0 ? i/o o i/o ? s tristate 63 99 pc[9] pcr[41] af0 af1 af2 af3 ? ? gpio[41] ? e0uc[7] ? lin2rx wkpu[13] (3) siul ? emios_0 ? linflex_2 wkpu i/o ? i/o ? i i s tristate 2 2 pc[10] pcr[42] af0 af1 af2 af3 gpio[42] ? ? ma[1] siul ? ? adc i/o ? ? o m tristate 13 22 pc[11] pcr[43] af0 af1 af2 af3 ? gpio[43] ? ? ma[2] wkpu[5] (3) siul ? ? adc wkpu i/o ? ? o i stristate ? 21 pc[12] pcr[44] af0 af1 af2 af3 ? gpio[44] e0uc[12] ? ? eirq[19] siul emios_0 ? ? siul i/o i/o ? ? i mtristate ? 97 pc[13] pcr[45] af0 af1 af2 af3 gpio[45] e0uc[13] ? ? siul emios_0 ? ? i/o i/o ? ? stristate ? 98 pc[14] pcr[46] af0 af1 af2 af3 ? gpio[46] e0uc[14] ? ? eirq[8] siul emios_0 ? ? siul i/o i/o ? ? i s tristate ? 3 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 spc560d30x, spc56040dx package pi nouts and signal descriptions doc id 16315 rev 7 23/90 pc[15] pcr[47] af0 af1 af2 af3 ? gpio[47] e0uc[15] ? ? eirq[20] siul emios_0 ? ? siul i/o i/o ? ? i m tristate ? 4 port d pd[0] pcr[48] af0 af1 af2 af3 ? ? gpio[48] ? ? ? wkpu[27] (3) adc1_p[4] siul ? ? ? wkpu adc i ? ? ? i i itristate ? 41 pd[1] pcr[49] af0 af1 af2 af3 ? ? gpio[49] ? ? ? wkpu[28] (3) adc1_p[5] siul ? ? ? wkpu adc i ? ? ? i i itristate ? 42 pd[2] pcr[50] af0 af1 af2 af3 ? gpio[50] ? ? ? adc1_p[6] siul ? ? ? adc i ? ? ? i itristate ? 43 pd[3] pcr[51] af0 af1 af2 af3 ? gpio[51] ? ? ? adc1_p[7] siul ? ? ? adc i ? ? ? i itristate ? 44 pd[4] pcr[52] af0 af1 af2 af3 ? gpio[52] ? ? ? adc1_p[8] siul ? ? ? adc i ? ? ? i itristate ? 45 pd[5] pcr[53] af0 af1 af2 af3 ? gpio[53] ? ? ? adc1_p[9] siul ? ? ? adc i ? ? ? i itristate ? 46 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 package pinouts and signal descriptions spc560d30x, spc56040dx 24/90 doc id 16315 rev 7 pd[6] pcr[54] af0 af1 af2 af3 ? gpio[54] ? ? ? adc1_p[10] siul ? ? ? adc i ? ? ? i itristate ? 47 pd[7] pcr[55] af0 af1 af2 af3 ? gpio[55] ? ? ? adc1_p[11] siul ? ? ? adc i ? ? ? i itristate ? 48 pd[8] pcr[56] af0 af1 af2 af3 ? gpio[56] ? ? ? adc1_p[12] siul ? ? ? adc i ? ? ? i itristate ? 49 pd[9] pcr[57] af0 af1 af2 af3 ? gpio[57] ? ? ? adc1_p[13] siul ? ? ? adc i ? ? ? i itristate ? 56 pd[10] pcr[58] af0 af1 af2 af3 ? gpio[58] ? ? ? adc1_p[14] siul ? ? ? adc i ? ? ? i itristate ? 57 pd[11] pcr[59] af0 af1 af2 af3 ? gpio[59] ? ? ? adc1_p[15] siul ? ? ? adc i ? ? ? i itristate ? 58 pd[12] pcr[60] af0 af1 af2 af3 ? gpio[60] cs5_0 e0uc[24] ? adc1_s[8] siul dspi_0 emios_0 ? adc i/o o i/o ? i jtristate ? 60 pd[13] pcr[61] af0 af1 af2 af3 ? gpio[61] cs0_1 e0uc[25] ? adc1_s[9] siul dspi_1 emios_0 ? adc i/o i/o i/o ? i jtristate ? 62 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 spc560d30x, spc56040dx package pi nouts and signal descriptions doc id 16315 rev 7 25/90 pd[14] pcr[62] af0 af1 af2 af3 ? gpio[62] cs1_1 e0uc[26] ? adc1_s[10] siul dspi_1 emios_0 ? adc i/o o i/o ? i jtristate ? 64 pd[15] pcr[63] af0 af1 af2 af3 ? gpio[63] cs2_1 e0uc[27] ? adc1_s[11] siul dspi_1 emios_0 ? adc i/o o i/o ? i jtristate ? 66 port e pe[0] pcr[64] af0 af1 af2 af3 ? gpio[64] e0uc[16] ? ? wkpu[6] (3) siul emios_0 ? ? wkpu i/o i/o ? ? i s tristate ? 6 pe[1] pcr[65] af0 af1 af2 af3 gpio[65] e0uc[17] ? ? siul emios_0 ? ? i/o i/o ? ? m tristate ? 8 pe[2] pcr[66] af0 af1 af2 af3 ? ? gpio[66] e0uc[18] ? ? eirq[21] sin_1 siul emios_0 ? ? siul dspi_1 i/o i/o ? ? i i mtristate ? 89 pe[3] pcr[67] af0 af1 af2 af3 gpio[67] e0uc[19] sout_1 ? siul emios_0 dspi_1 ? i/o i/o o ? mtristate ? 90 pe[4] pcr[68] af0 af1 af2 af3 ? gpio[68] e0uc[20] sck_1 ? eirq[9] siul emios_0 dspi_1 ? siul i/o i/o i/o ? i mtristate ? 93 pe[5] pcr[69] af0 af1 af2 af3 gpio[69] e0uc[21] cs0_1 ma[2] siul emios_0 dspi_1 adc i/o i/o i/o o mtristate ? 94 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 package pinouts and signal descriptions spc560d30x, spc56040dx 26/90 doc id 16315 rev 7 pe[6] pcr[70] af0 af1 af2 af3 ? gpio[70] e0uc[22] cs3_0 ma[1] eirq[22] siul emios_0 dspi_0 adc siul i/o i/o o o i mtristate ? 95 pe[7] pcr[71] af0 af1 af2 af3 ? gpio[71] e0uc[23] cs2_0 ma[0] eirq[23] siul emios_0 dspi_0 adc siul i/o i/o o o i mtristate ? 96 pe[8] pcr[72] af0 af1 af2 af3 gpio[72] ? e0uc[22] ? siul ? emios_0 ? i/o ? i/o ? m tristate ? 9 pe[9] pcr[73] af0 af1 af2 af3 ? gpio[73] ? e0uc[23] ? wkpu[7] (3) siul ? emios_0 ? wkpu i/o ? i/o ? i stristate ? 10 pe[10] pcr[74] af0 af1 af2 af3 ? gpio[74] ? cs3_1 ? eirq[10] siul ? dspi_1 ? siul i/o ? o ? i stristate ? 11 pe[11] pcr[75] af0 af1 af2 af3 ? gpio[75] e0uc[24] cs4_1 ? wkpu[14] (3) siul emios_0 dspi_1 ? wkpu i/o i/o o ? i stristate ? 13 pe[12] pcr[76] af0 af1 af2 af3 ? ? gpio[76] ? ? ? adc1_s[7] eirq[11] siul ? ? ? adc siul i/o ? ? ? i i stristate ? 76 port h table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 spc560d30x, spc56040dx package pi nouts and signal descriptions doc id 16315 rev 7 27/90 ph[9] (6) pcr[121] af0 af1 af2 af3 gpio[121] ? tck ? siul ? jtagc ? i/o ? i ? s input, weak pull-up 60 88 ph[10] (6 ) pcr[122] af0 af1 af2 af3 gpio[122] ? tms ? siul ? jtagc ? i/o ? i ? s input, weak pull-up 53 81 1. alternate functions are chosen by setting the values of the pcr.pa bitfields inside the siul module. pcr.pa = 00 ? af0; pcr.pa = 01 ? af1; pcr.pa = 10 ? af2; pcr.pa = 11 ? af3. this is intended to select the output functions; to use one of the input functions, the pcr.ibe bit mu st be written to ?1?, regardless of the values selected in the pcr.pa bitfields. for this reason, the value corresponding to an input only function is reported as ???. 2. multiple inputs are routed to all respective modules internal ly. the input of some modules must be configured by setting the values of the psmio.padselx bitfields inside the siul module. 3. all wkpu pins also support external interrupt capability. see ?wakeup unit? c hapter of the device reference manual for further details. 4. nmi has higher priority than alternate function. w hen nmi is selected, the pcr.af field is ignored. 5. ?not applicable? because these functions are available only wh ile the device is booting. refer to ?bam? chapter of the device reference manual for details. 6. out of reset all the functional pins except pc[0:1 ] and ph[9:10] are available to the user as gpio. pc[0:1] are available as jtag pins (tdi and tdo respectively). ph[9:10] are available as jtag pins (tck and tms respectively). if the user configures these jtag pins in gpio mode the device is no longer compliant with ieee 1149.1 2001. table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 electrical characteristics spc560d30x, spc56040dx 28/90 doc id 16315 rev 7 4 electrical characteristics 4.1 introduction this section contains electrical characteristics of the device as well as temperature and power considerations. this product contains devices to protect the inputs against damage due to high static voltages. however, it is advisable to take precautions to avoid application of any voltage higher than the specified maximum rated voltages. to enhance reliability, unused inputs can be driven to an appr opriate logic voltage level (v dd or v ss ). this can be done by the internal pull-up or pull-down, which is provided by the product for most general purpose pins. the parameters listed in the following tables represent the characteristics of the device and its demands on the system. in the tables where the device logic provides signals with their respective timing characteristics, the symbol ?cc? for controller characteristics is included in the symbol column. in the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol ?sr? for system requirement is included in the symbol column. 4.2 parameter classification the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding, the classifications listed in ta b l e 7 are used and the parameters are tagged accordingly in the tables where appropriate. note: the classification is shown in the column labeled ?c? in the parameter tables where appropriate. table 7. parameter classifications classification tag tag description p those parameters are guaranteed during production testing on each individual device. c those parameters are achieved by the design c haracterization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwi se noted. all values shown in the typical column are within this category. d those parameters are derived mainly from simulations. spc560d30x, spc56040dx electrical characteristics doc id 16315 rev 7 29/90 4.3 nvusro register bit values in the non- volatile user options (nvusro) re gister control portions of the device configuration, namely electrical parameters such as high voltage supply and oscillator margin, as well as digital functi onality (watchdog enable/disable after reset). for a detailed description of the nvusro register, please refer to the device reference manual. 4.3.1 nvusro[pad3v5v] field description the dc electrical characteristics are dependent on the pad3v5v bit value. ta bl e 8 shows how nvusro[pad3v5v] controls the device configuration. 4.3.2 nvusro[oscillator_m argin] field description the fast external crystal oscillato r consumption is dependent on the oscillator_margin bit value. ta b l e 9 shows how nvusro[oscillator_margin] controls the device configuration. 4.3.3 nvusro[watchdog_en] field description the watchdog enable/disable configuration after reset is dependent on the watchdog_en bit value. ta bl e 9 shows how nvusro[watchdog_en] controls the device configuration. table 8. pad3v5v field description value (1) 1. default manufacturing value is ?1?. value can be programmed by customer in shadow flash. description 0 high voltage supply is 5.0 v 1 high voltage supply is 3.3 v table 9. oscillator_margin field description value (1) 1. default manufacturing value is ?1?. value can be programmed by customer in shadow flash. description 0 low consumption configuration (4 mhz/8 mhz) 1 high margin configuration (4 mhz/16 mhz) table 10. watchdog_en field description value (1) 1. default manufacturing value is ?1?. value can be programmed by customer in shadow flash. description 0 disable after reset 1 enable after reset electrical characteristics spc560d30x, spc56040dx 30/90 doc id 16315 rev 7 4.4 absolute maximum ratings note: stresses exceeding the recommended absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification are not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. during overload conditions (v in >v dd or v in electrical characteristics spc560d30x, spc56040dx 32/90 doc id 16315 rev 7 note: sram data retention is guaranteed with v dd_lv not below 1.08 v. v ss_lv (3) sr ? voltage on vss_lv (low voltage digital supply) pins with respect to ground (v ss ) ?v ss ? 0.1 v ss +0.1 v v dd_bv (4) sr ? voltage on vdd_bv pin (regulator supply) with respect to ground (v ss ) ?4.55.5 v voltage drop (2) 3.0 5.5 relative to v dd v dd ? 0.1 v dd +0.1 v ss_adc sr ? voltage on vss_hv_adc (adc reference) pin with respect to ground (v ss ?v ss ? 0.1 v ss +0.1 v v dd_adc (5) sr ? voltage on vdd_hv_adc pin (adc reference) with respect to ground (v ss ) ?4.55.5 v voltage drop (2) 3.0 5.5 relative to v dd v dd ? 0.1 v dd +0.1 v in sr ? voltage on any gpio pin with respect to ground (v ss ) ?v ss ? 0.1 ? v relative to v dd ?v dd +0.1 i injpad sr ? injected input current on any pin during overload condition ? ? 55ma i injsum sr ? absolute sum of all injected input currents during overload condition ? ? 50 50 ma tv dd sr ? v dd slope to ensure correct power up (6) ?3.0 (7) 250 x 10 3 (0.25 [v/s]) v/s 1. 100 nf capacitance needs to be provided between each v dd /v ss pair. 2. full device operation is guaranteed by design when the volt age drops below 4.5 v down to 3.6 v. however, certain analog electrical characteri stics will not be guaranteed to stay within the stated limits. 3. 330 nf capacitance needs to be provided between each v dd_lv /v ss_lv supply pair. 4. 470 nf capacitance needs to be provided between v dd_bv and the nearest v ss_lv (higher value may be needed depending on external regul ator characteristics). 5. 100 nf capacitance needs to be provided between v dd_adc /v ss_adc pair. 6. guaranteed by device validation 7. minimum value of tv dd must be guaranteed until v dd reaches 2.6 v (maximum value of v porh ) table 13. recommended operating conditions (5.0 v) (continued) symbol c parameter conditions value unit min max spc560d30x, spc56040dx electrical characteristics doc id 16315 rev 7 33/90 4.6 thermal characteristics 4.6.1 package thermal characteristics 4.6.2 power considerations the average chip-junction temperature, t j , in degrees celsius, may be calculated using equation 1 : table 14. lqfp thermal characteristics (1) symbol c parameter conditions (2) value unit r ? ja cc d thermal resistance, junction-to-ambient natural convection (3) single-layer board ?1s lqfp64 72.1 c/w lqfp100 65.2 four-layer board ? 2s2p lqfp64 57.3 lqfp100 51.8 r ? jb cc d thermal resistance, junction-to-board (4) four-layer board ? 2s2p lqfp64 44.1 c/w lqfp100 41.3 r ? jc cc d thermal resistance, junction-to-case (5) single-layer board ? 1s lqfp64 26.5 c/w lqfp100 23.9 four-layer board ? 2s2p lqfp64 26.2 lqfp100 23.7 ? jb cc d junction-to-board thermal characterization parameter, natural convection single-layer board ? 1s lqfp64 41 c/w lqfp100 41.6 four-layer board ? 2s2p lqfp64 43 lqfp100 43.4 ? jc cc d junction-to-case thermal characterization parameter, natural convection single-layer board ? 1s lqfp64 11.5 c/w lqfp100 10.4 four-layer board ? 2s2p lqfp64 11.1 lqfp100 10.2 1. thermal characteristics ar e targets based on simulation that are s ubject to change per devic e characterization. 2. v dd = 3.3 v 10% / 5.0 v 10%, t a = ?40 to 125 c 3. junction-to-ambient thermal resist ance determined per jedec jesd51-3 and jesd51-7. thermal test board meets jedec specification for this package. when greek letters are not avail able, the symbols are typed as r thja . 4. junction-to-board thermal resistance det ermined per jedec jesd51-8. thermal test board meets jedec specification for the specified package. when greek letters are not available, the symbols are typed as r thjb . 5. junction-to-case at the top of the package determined using mil-std 883 method 1012.1. the cold plate temperature is used for the case temperature. reported value includes the t hermal resistance of the interface layer. when greek letters are not available, the symbols are typed as r thjc . electrical characteristics spc560d30x, spc56040dx 34/90 doc id 16315 rev 7 equation 1 t j = t a + (p d x r ? ja ) where: t a is the ambient temperature in c. r ? ja is the package junction-to-ambient thermal resistance, in c/w. p d is the sum of p int and p i/o (p d = p int + p i/o ). p int is the product of i dd and v dd , expressed in watts. this is the chip internal power. p i/o represents the power dissipation on input and output pins; user determined. most of the time for the applications, p i/o < p int and may be neglected. on the other hand, p i/o may be significant, if the device is configured to continuously drive external modules and/or memories. an approximate relationship between p d and t j (if p i/o is neglected) is given by: equation 2 p d = k / (t j + 273 c) therefore, solving equations 1 and 2 : equation 3 k = p d x (t a + 273 c) + r ? ja x p d 2 where: k is a constant for the particular part, which may be determined from equation 3 by measuring p d (at equilibrium) for a known t a. using this value of k, the values of p d and t j may be obtained by solving equations 1 and 2 iteratively for any value of t a . 4.7 i/o pad electrical characteristics 4.7.1 i/o pad types the device provides four main i/o pad ty pes depending on the associated alternate functions: slow pads?these pads are the most common pads, providing a good compromise between transition time and low electromagnetic emission. medium pads?these pads provide transition fast enough for the serial communication channels with controlled current to reduce electromagnetic emission. input only pads?these pads are associated to adc channels (adc_p[x]) providing low input leakage. medium pads can use slow configuration to re duce electromagnetic emission except for pc[1], that is medium only, at the cost of reducing ac performance. 4.7.2 i/o input dc characteristics ta bl e 1 5 provides input dc electrical ch aracteristics as described in figure 4 . spc560d30x, spc56040dx electrical characteristics doc id 16315 rev 7 35/90 figure 4. input dc electrical characteristics definition v il v in v ih pdix = ?1? v dd v hys (gpdi register of siul) pdix = ?0? table 15. i/o input dc electrical characteristics symbol c parameter conditions (1) value unit min typ max v ih sr p input high level cmos (schmitt trigger) ? 0.65v dd ?v dd +0.4 v v il sr p input low level cmos (schmitt trigger) ? ? 0.4 ? 0.35v dd v v hys cc c input hysteresis cmos (schmitt trigger) ?0.1v dd ??v i lkg cc d digital input leakage no injection on adjacent pin t a = ? 40 c ? 2 200 na dt a = 25 c ? 2 200 dt a = 85 c ? 5 300 dt a = 105 c ? 12 500 pt a = 125 c ? 70 1000 w fi (2) sr p digital input filtered pulse ? ? ? 40 ns w nfi (2) sr p digital input not filtered pulse ? 1000 ? ? ns 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2. in the range from 40 to 1000 ns, pulses can be filtered or not filtered, according to oper ating temperature and voltage. electrical characteristics spc560d30x, spc56040dx 36/90 doc id 16315 rev 7 4.7.3 i/o output dc characteristics the following tables provide dc characteristics for bidirectional pads: ta bl e 1 6 provides weak pull figures. both pull-up and pull-down resistances are supported. ta bl e 1 7 provides output driver characteristics for i/o pads when in slow configuration. ta bl e 1 8 provides output driver characteristics for i/o pads when in medium configuration. table 16. i/o pull-up/pull-down dc electrical characteristics symbol c parameter conditions (1) value unit min typ max |i wpu |cc p weak pull-up current absolute value v in = v il , v dd = 5.0 v 10% pad3v5v = 0 10 ? 150 a c pad3v5v = 1 (2) 10 ? 250 pv in = v il , v dd = 3.3 v 10% pad3v5v = 1 10 ? 150 |i wpd |cc p weak pull-down current absolute value v in = v ih , v dd = 5.0 v 10% pad3v5v = 0 10 ? 150 a c pad3v5v = 1 (2) 10 ? 250 pv in = v ih , v dd = 3.3 v 10% pad3v5v = 1 10 ? 150 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2. the configuration pad3v5 = 1 when v dd = 5 v is only a transient configuration during power-up. all pads but reset are configured in input or in high impedance state. table 17. slow configuration output buffer electrical characteristics symbol c parameter conditions (1) value unit min typ max v oh cc p output high level slow configuration push pull i oh = ? 2ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) 0.8v dd ?? v c i oh = ? 2ma, v dd = 5.0 v 10%, pad3v5v = 1 (2) 0.8v dd ?? c i oh = ? 1ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) v dd ? 0.8 ? ? v ol cc p output low level slow configuration push pull i ol = 2 ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) ? ? 0.1v dd v c i ol = 2 ma, v dd = 5.0 v 10%, pad3v5v = 1 (2) ? ? 0.1v dd c i ol = 1 ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) ??0.5 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified spc560d30x, spc56040dx electrical characteristics doc id 16315 rev 7 37/90 2. the configuration pad3v5 = 1 when v dd = 5 v is only a transient configuration during power-up. all pads but reset are configured in input or in high impedance state. table 18. medium configuration output buffer electrical characteristics symbol c parameter conditions (1) value unit min typ max v oh cc c output high level medium configuration push pull i oh = ? 3.8 ma, v dd = 5.0 v 10%, pad3v5v = 0 0.8v dd ?? v p i oh = ? 2ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) 0.8v dd ?? c i oh = ? 1ma, v dd = 5.0 v 10%, pad3v5v = 1 (2) 0.8v dd ?? c i oh = ? 1ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) v dd ? 0.8 ? ? c i oh = ? 100 a, v dd = 5.0 v 10%, pad3v5v = 0 0.8v dd ?? v ol cc c output low level medium configuration push pull i ol = 3.8 ma, v dd = 5.0 v 10%, pad3v5v = 0 ??0.2v dd v p i ol = 2 ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) ??0.1v dd c i ol = 1 ma, v dd = 5.0 v 10%, pad3v5v = 1 (2) ??0.1v dd c i ol = 1 ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) ??0.5 c i ol = 100 a, v dd = 5.0 v 10%, pad3v5v = 0 ??0.1v dd 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2. the configuration pad3v5 = 1 when v dd = 5 v is only a transient configuration during power-up. all pads but reset are configured in input or in high impedance state. electrical characteristics spc560d30x, spc56040dx 38/90 doc id 16315 rev 7 4.7.4 output pin transition times 4.7.5 i/o pad current specification the i/o pads are distributed across the i/o supply segment. each i/o supply segment is associated to a v dd /v ss supply pair as described in ta bl e 2 0 . ta bl e 2 1 provides i/o consumption figures. in order to ensure device relia bility, the average current of the i/o on a single segment should remain below the i avgseg maximum value. table 19. output pin transition times symbol c parameter conditions (1) value unit min typ max t tr cc d output transition time output pin (2) slow configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ??50 ns tc l = 50 pf ? ? 100 dc l = 100 pf ? ? 125 dc l = 25 pf v dd = 3.3 v 10%, pad3v5v = 1 ??50 tc l = 50 pf ? ? 100 dc l = 100 pf ? ? 125 t tr cc d output transition time output pin (2) medium configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 siul.pcrx.src = 1 ??10 ns tc l = 50 pf ? ? 20 dc l = 100 pf ? ? 40 dc l = 25 pf v dd = 3.3 v 10%, pad3v5v = 1 siul.pcrx.src = 1 ??12 tc l = 50 pf ? ? 25 dc l = 100 pf ? ? 40 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2. c l includes device and package capacitances (c pkg < 5 pf). table 20. i/o supply segment package supply segment 1234 lqfp100 pin 16 ? pin 35 pin 37 ? pin 69 pin 70 ? pin 83 pin 84 ? pin 15 lqfp64 pin 8 ? pin 26 pin 28 ? pin 55 pin 56 ? pin 7 ? spc560d30x, spc56040dx electrical characteristics doc id 16315 rev 7 39/90 ta bl e 2 2 provides the weight of concurrent switching i/os. in order to ensure device functionality, the sum of the weight of concurrent switching i/os on a single segment should remain below 100%. table 21. i/o consumption symbol c parameter conditions (1) value unit min typ max i swtslw (2) cc d dynamic i/o current for slow configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ??20 ma v dd = 3.3 v 10%, pad3v5v = 1 ??16 i swtmed (2) cc d dynamic i/o current for medium configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ??29 ma v dd = 3.3 v 10%, pad3v5v = 1 ??17 i rmsslw cc d root mean square i/o current for slow configuration c l = 25 pf, 2 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??2.3 ma c l = 25 pf, 4 mhz ? ? 3.2 c l = 100 pf, 2 mhz ? ? 6.6 c l = 25 pf, 2 mhz v dd = 3.3 v 10%, pad3v5v = 1 ??1.6 c l = 25 pf, 4 mhz ? ? 2.3 c l = 100 pf, 2 mhz ? ? 4.7 i rmsmed cc d root mean square i/o current for medium configuration c l = 25 pf, 13 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??6.6 ma c l = 25 pf, 40 mhz ? ? 13.4 c l = 100 pf, 13 mhz ? ? 18.3 c l = 25 pf, 13 mhz v dd = 3.3 v 10%, pad3v5v = 1 ?? 5 c l = 25 pf, 40 mhz ? ? 8.5 c l = 100 pf, 13 mhz ? ? 11 i avgseg sr d sum of all the static i/o current within a supply segment v dd = 5.0 v 10%, pad3v5v = 0 ? ? 70 ma v dd = 3.3 v 10%, pad3v5v = 1 ? ? 65 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2. stated maximum values represent peak consumption that lasts only a few ns during i/o transition. table 22. i/o weight (1) pad lqfp100/lqfp64 weight 5 v weight 3.3 v src (2) = 0 src = 1 src = 0 src = 1 pb[3] 9% 9% 10% 10% pc[9] 8% 8% 10% 10% electrical characteristics spc560d30x, spc56040dx 40/90 doc id 16315 rev 7 pc[14] 8% 8% 10% 10% pc[15] 8% 11% 9% 10% pa[2]8%8%9%9% pe[0] 7% 7% 9% 9% pa[1]7%7%8%8% pe[1] 7% 10% 8% 8% pe[8] 6% 9% 8% 8% pe[9] 6% 6% 7% 7% pe[10] 6% 6% 7% 7% pa[0]5%7%6%7% pe[11] 5% 5% 6% 6% pc[11] 7% 7% 9% 9% pc[10] 8% 11% 9% 10% pb[0] 8% 11% 9% 10% pb[1] 8% 8% 10% 10% pc[6] 8% 8% 10% 10% pc[7] 8% 8% 10% 10% pa[15] 8% 11% 9% 10% pa[14] 7% 11% 9% 9% pa[4]7%7%8%8% pa[13] 7% 10% 8% 9% pa[12] 7% 7% 8% 8% pb[9] 1% 1% 1% 1% pb[8] 1% 1% 1% 1% pb[10] 5% 5% 6% 6% pd[0]1%1%1%1% pd[1]1%1%1%1% pd[2]1%1%1%1% pd[3]1%1%1%1% pd[4]1%1%1%1% pd[5]1%1%1%1% pd[6]1%1%1%1% table 22. i/o weight (1) (continued) pad lqfp100/lqfp64 weight 5 v weight 3.3 v src (2) = 0 src = 1 src = 0 src = 1 spc560d30x, spc56040dx electrical characteristics doc id 16315 rev 7 41/90 pd[7]1%1%1%1% pd[8]1%1%1%1% pb[4] 1% 1% 1% 1% pb[5] 1% 1% 1% 1% pb[6] 1% 1% 1% 1% pb[7] 1% 1% 1% 1% pd[9]1%1%1%1% pd[10] 1% 1% 1% 1% pd[11] 1% 1% 1% 1% pb[11] 9% 9% 11% 11% pd[12] 8% 8% 10% 10% pb[12] 8% 8% 10% 10% pd[13] 8% 8% 9% 9% pb[13] 8% 8% 9% 9% pd[14] 7% 7% 9% 9% pb[14] 7% 7% 8% 8% pd[15] 7% 7% 8% 8% pb[15] 6% 6% 7% 7% pa[3]6%6%7%7% pa[7]4%4%5%5% pa[8]4%4%5%5% pa[9]4%4%5%5% pa[10] 5% 5% 6% 6% pa[11] 5% 5% 6% 6% pe[12] 5% 5% 6% 6% pc[3]5%5%6%6% pc[2]5%7%6%6% pa[5]5%6%5%6% pa[6]4%4%5%5% pc[1] 5% 17% 4% 12% pc[0]6%9%7%8% pe[2] 7% 10% 8% 9% table 22. i/o weight (1) (continued) pad lqfp100/lqfp64 weight 5 v weight 3.3 v src (2) = 0 src = 1 src = 0 src = 1 electrical characteristics spc560d30x, spc56040dx 42/90 doc id 16315 rev 7 4.8 reset electrical characteristics the device implements a de dicated bidirectional reset pin. figure 5. start-up reset requirements pe[3] 7% 10% 9% 9% pc[5] 8% 11% 9% 10% pc[4] 8% 11% 9% 10% pe[4] 8% 12% 10% 10% pe[5] 8% 12% 10% 11% pe[6] 9% 12% 10% 11% pe[7] 9% 12% 10% 11% pc[12] 9% 13% 11% 11% pc[13] 9% 9% 11% 11% pc[8] 9% 9% 11% 11% pb[2] 9% 13% 11% 12% 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2. src: ?slew rate control? bit in siu_pcr table 22. i/o weight (1) (continued) pad lqfp100/lqfp64 weight 5 v weight 3.3 v src (2) = 0 src = 1 src = 0 src = 1 v il v dd device reset forced by reset v ddmin reset v ih device start-up phase spc560d30x, spc56040dx electrical characteristics doc id 16315 rev 7 43/90 figure 6. noise filtering on reset signal v reset v il v ih v dd filtered by hysteresis filtered by lowpass filter w frst w nfrst hw_rst ?1? ?0? filtered by lowpass filter w frst unknown reset state device under hardware reset table 23. reset electrical characteristics symbol c parameter conditions (1) value unit min typ max v ih sr p input high level cmos (schmitt trigger) ? 0.65v dd ?v dd +0.4 v v il sr p input low level cmos (schmitt trigger) ? ? 0.4 ? 0.35v dd v v hys cc c input hysteresis cmos (schmitt trigger) ?0.1v dd ??v v ol cc p output low level push pull, i ol = 2 ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) ? ? 0.1v dd v push pull, i ol = 1 ma, v dd = 5.0 v 10%, pad3v5v = 1 (2) ? ? 0.1v dd push pull, i ol = 1 ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) ??0.5 electrical characteristics spc560d30x, spc56040dx 44/90 doc id 16315 rev 7 4.9 power management electrical characteristics 4.9.1 voltage regulator electrical characteristics the device implements an internal voltage regulator to generate the low voltage core supply v dd_lv from the high voltage ballast supply v dd_bv . the regulator itself is supplied by the common i/o supply v dd . the following supplies are involved: hv: high voltage external power supply for voltage regulator module. this must be provided externally through v dd power pin. bv: high voltage external power supply for internal ballast module. this must be provided externally through v dd_bv power pin. voltage values should be aligned with v dd . lv: low voltage internal power supply for core, fmpll and flash digital logic. this is generated by the internal volt age regulator but provided outside to connect stability t tr cc d output transition time output pin (3) medium configuration c l = 25 pf, v dd = 5.0 v 10%, pad3v5v = 0 ??10 ns c l = 50 pf, v dd = 5.0 v 10%, pad3v5v = 0 ??20 c l = 100 pf, v dd = 5.0 v 10%, pad3v5v = 0 ??40 c l = 25 pf, v dd = 3.3 v 10%, pad3v5v = 1 ??12 c l = 50 pf, v dd = 3.3 v 10%, pad3v5v = 1 ??25 c l = 100 pf, v dd = 3.3 v 10%, pad3v5v = 1 ??40 w frst sr p reset input filtered pulse ???40ns w nfrst sr p reset input not filtered pulse ? 1000 ? ? ns |i wpu |ccp weak pull-up current absolute value v dd = 3.3 v 10%, pad3v5v = 1 10 ? 150 a v dd = 5.0 v 10%, pad3v5v = 0 10 ? 150 v dd = 5.0 v 10%, pad3v5v = 1 (4) 10 ? 250 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2. this is a transient configuration duri ng power-up, up to the end of reset phase2 (refer to rgm module section of the device reference manual). 3. c l includes device and package capacitance (c pkg <5pf). 4. the configuration pad3v5 = 1 when v dd = 5 v is only transient configuration during power-up. all pads but reset are configured in input or in high impedance state. table 23. reset electrical characteristics (continued) symbol c parameter conditions (1) value unit min typ max spc560d30x, spc56040dx electrical characteristics doc id 16315 rev 7 45/90 capacitor. it is further split into four main domains to ensure noise isolation between critical lv modules within the device: ? lv_cor: low voltage supply for the core. it is also used to provide supply for fmpll through double bonding. ? lv_cfla: low voltage supply for code flash module. it is supplied with dedicated ballast and shorted to lv_cor through double bonding. ? lv_dfla: low voltage supply for data flash module. it is supplied with dedicated ballast and shorted to lv_cor through double bonding. ? lv_pll: low voltage supply for fmpll. it is shorted to lv_cor through double bonding. figure 7. voltage regulator capacitance connection the internal voltage regulator requires external capacitance (c regn ) to be connected to the device in order to provide a stable low voltage digital supply to the device. capacitances should be placed on the board as near as possible to the associated pins. care should also be taken to limit the serial inductance of the board to less than 5 nh. each decoupling capacitor must be placed between each of the three v dd_lv /v ss_lv supply pairs to ensure stable voltage (see section 4.5, recommended operating conditions ). c reg1 (lv_cor/lv_dfla) device v ss_lv v dd_bv v dd_lv c dec1 (ballast decoupling) v ss_lv v dd_lv v dd v ss_lv v dd_lv c reg2 (lv_cor/lv_cfla) c reg3 c dec2 device v dd_bv i v dd_lvn v ref v dd voltage regulator v ss v ss_lvn (supply/io decoupling) (lv_cor/lv_pll) electrical characteristics spc560d30x, spc56040dx 46/90 doc id 16315 rev 7 table 24. voltage regulator electrical characteristics symbol c parameter conditions (1) value unit min typ max c regn sr ? internal voltage regulator external capacitance ? 200 ? 500 nf r reg sr ? stability capacitor equivalent serial resistance range: 10 khz to 20 mhz ??0.2 ? c dec1 sr ? decoupling capacitance (2) ballast v dd_bv /v ss_lv pair: v dd_bv = 4.5 v to 5.5 v 100 (3) 470 (4) ? nf v dd_bv /v ss_lv pair: v dd_bv = 3v to 3.6v 400 ? c dec2 sr ? decoupling capacitance regulator supply v dd /v ss pair 10 100 ? nf v mreg cc t main regulator output voltage before exiting from reset ? 1.32 ? v p after trimming 1.16 1.28 ? i mreg sr ? main regulator current provided to v dd_lv domain ??? 150 ma i mregint cc d main regulator module current consumption i mreg = 200 ma ? ? 2 ma i mreg = 0 ma ? ? 1 v lpreg cc p low-power regulator output voltage after trimming 1.16 1.28 ? v i lpreg sr ? low power regulator current provided to v dd_lv domain ??? 15 ma i lpregint cc d low-power regulator module current consumption i lpreg = 15 ma; t a = 55 c ?? 600 a ? i lpreg = 0 ma; t a = 55 c ? 5 ? v ulpreg cc p ultra low power regulator output voltage after trimming 1.16 1.28 ? v i ulpreg sr ? ultra low power regulator current provided to v dd_lv domain ??? 5 ma i ulpregint cc d ultra low power regulator module current consumption i ulpreg = 5 ma; t a = 55 c ?? 100 a i ulpreg = 0 ma; t a = 55 c ? 2 ? i dd_bv cc d in-rush average current on v dd_bv during power-up (5) ?? ? 300 (6) ma 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2. this capacitance value is driven by the constraints of the ex ternal voltage regulator supplying the v dd_bv voltage. a typical value is in the range of 470 nf. 3. this value is acceptable to guar antee operation from 4.5 v to 5.5 v. 4. external regulator and capacitance ci rcuitry must be capabl e of providing i dd_bv while maintaining supply v dd_bv in operating range. 5. in-rush average current is seen only for short time during power-up and on st andby exit (maximum 20 s, depending on external capacitances to be loaded). spc560d30x, spc56040dx electrical characteristics doc id 16315 rev 7 47/90 4.9.2 low voltage detector el ectrical characteristics the device implements a power-on reset (por) module to ensure correct power-up initialization, as well as five low volt age detectors (lvds) to monitor the v dd and the v dd_lv voltage while device is supplied: por monitors v dd during the power-up phase to ensure device is maintained in a safe reset state (refer to rgm destructive event status (rgm_des) register flag f_por in device reference manual) lvdhv3 monitors v dd to ensure device reset below minimum functional supply (refer to rgm destructive event status (rgm_des) register flag f_lvd27 in device reference manual) lvdhv3b monitors v dd_bv to ensure device reset below minimum functional supply (refer to rgm destructive event status (rgm_des) register flag f_lvd27_vreg in device reference manual) lvdhv5 monitors v dd when application uses device in the 5.0 v 10% range (refer to rgm functional event status (rgm_fes) register flag f_lvd45 in device reference manual) lvdlvcor monitors power domain no. 1 (refer to rgm destructive event status (rgm_des) register flag f_lvd12_pd1 in device reference manual) lvdlvbkp monitors power domain no. 0 (r efer to rgm destructive event status (rgm_des) register flag f_lvd12_pd0 in device reference manual) figure 8. low voltage detector vs reset 6. the duration of the in-rush current depends on the capacitanc e placed on lv pins. bv decouplin g capacitors must be sized accordingly. refer to i mreg value for minimum amount of current to be provided in cc. v dd v lvdhvxh reset v lvdhvxl electrical characteristics spc560d30x, spc56040dx 48/90 doc id 16315 rev 7 4.10 power consumption ta bl e 2 6 provides dc electrical characteristi cs for significant application modes. these values are indicative values; actual consumption depends on the application. table 25. low voltage detector electrical characteristics symbol c parameter conditions (1) value unit min typ max v porup sr p supply for functional por module t a = 25 c, after trimming 1.0 ? 5.5 v v porh cc p power-on reset threshold 1.5 ? 2.6 v v lv d h v 3 h cc t lvdhv3 low voltage detector high threshold ? ? 2.95 v v lv d h v 3 l cc p lvdhv3 low voltage detector low threshold 2.6 ? 2.9 v v lvdhv3bh cc p lvdhv3b low voltage detector high threshold ? ? 2.95 v v lvdhv3bl cc p lvdhv3b low voltage detector low threshold 2.6 ? 2.9 v v lv d h v 5 h cc t lvdhv5 low voltage detector high threshold ? ? 4.5 v v lv d h v 5 l cc p lvdhv5 low voltage detector low threshold 3.8 ? 4.4 v v lv d lv c o r l cc p lvdlvcor low voltage detector low threshold 1.08 ? 1.16 v v lvdlvbkpl cc p lvdlvbkp low voltage detector low threshold 1.08 ? 1.16 v 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified table 26. power consumption on vdd_bv and vdd_hv symbol c parameter conditions (1) value unit min typ max i ddmax (2) cc d run mode maximum average current ? ? 90 130 (3) ma i ddrun (4) cc t run mode typical average current (5) f cpu = 8 mhz ? 7 ? ma tf cpu = 16 mhz ? 18 ? tf cpu = 32 mhz ? 29 ? pf cpu = 48 mhz ? 40 100 i ddhalt cc c halt mode current (6) slow internal rc oscillator (128 khz) running t a =25c ? 8 15 ma pt a = 125 c ? 14 25 i ddstop cc p stop mode current (7) slow internal rc oscillator (128 khz) running t a = 25 c ? 180 700 (8) a dt a = 55 c ? 500 ? dt a =85c ? 1 6 (8) ma dt a = 105 c ? 2 9 (8) pt a = 125 c ? 4.5 12 (8) spc560d30x, spc56040dx electrical characteristics doc id 16315 rev 7 49/90 4.11 flash memory electrical characteristics the data flash operation depends strongly on the code flash operation. if code flash is switched-off, the data flash is disabled. 4.11.1 program/erase characteristics ta bl e 2 7 shows the program and erase characteristics. i ddstdby cc p standby mode current (9) slow internal rc oscillator (128 khz) running t a = 25 c ? 30 100 a dt a =55c ? 75 ? dt a = 85 c ? 180 700 dt a = 105 c ? 315 1000 pt a = 125 c ? 560 1700 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2. running consumption does not include i/os toggling which is highly dependent on the application. the given value is thought to be a worst case value with all peripherals running, and code fetched from code flash while modify operation ongoing on data flash. notice that this value can be signific antly reduced by application: sw itch off not used peripherals (default), reduce peripheral frequency th rough internal prescaler, fetch from ram most used functions, use low power mode when possible. 3. higher current may be sinked by device during power-up and standby exit. plea se refer to in-rush average current on table 24 . 4. run current measured with ty pical application with accesses on both flash memory and sram. 5. only for the ?p? classification: code fetched from sram: se rial ips can and lin in loop-back mode, dspi as master, pll as system clock (3 multiplier) peri pherals on (emios/ctu/adc) and running at maximum frequency, periodic sw/wdg timer reset enabled. 6. data flash power down. code flash in low power. sirc (128 khz) and firc (16 mhz) on. 10 mhz xtal clock. flexcan: 0 on (clocked but no reception or transmission) . linflex: instances: 0, 1, 2 on (clo cked but no reception or transmission), instance: 3 clocks gated. emios: instance: 0 on (16 channels on pa[0]?pa[11] and pc[12]?pc[15]) with pwm 20 khz, instance: 1 clock gated. dspi: instance: 0 (clocked but no communication). rtc/api on.pit on. stm on. adc on but no conversion except 2 analog watchdogs. 7. only for the ?p? classification: no clock, firc (16 mhz) off, sirc (128 khz) on, pll off, hpvreg off, ulpvreg/lpvreg on. all possible peripherals o ff and clock gated. flash in power down mode. 8. when going from run to stop mode and the core consumption is > 6 ma, it is normal operation for the main regulator module to be kept on by the on-chip current monitoring circuit. this is most likely to occur with junction temperatures exceeding 125 c and under these circumstanc es, it is possible for the current to initially exceed the maximum stop specification by up to 2 ma. after enter ing stop, the application junction temperat ure will reduce to the ambient level and the main regulator will be automatically swit ched off when the load current is below 6 ma. 9. only for the ?p? classification: ulpvreg on, hp/lpvreg off, 16 kb sram on, device configured for minimum consumption, all possible modules switched off. table 26. power consumption on vdd_bv and vdd_hv (continued) symbol c parameter conditions (1) value unit min typ max table 27. program and erase specifications (code flash) symbol c parameter value unit min typ (1) initial max (2) max (3) t dwprogram cc c double word (64 bits) program time (4) ?2250500s t 16kpperase cc c 16 kb block preprogram and erase time ? 300 500 5000 ms electrical characteristics spc560d30x, spc56040dx 50/90 doc id 16315 rev 7 t 32kpperase cc c 32 kb block preprogram and erase time ? 400 600 5000 ms t 128kpperase cc c 128 kb block preprogram and erase time ? 800 1300 7500 ms t esus cc c erase suspend latency ? ? 30 30 s 1. typical program and erase ti mes assume nominal supply values and operati on at 25 c. all times are subject to change pending device characterization. 2. initial factory condition: < 100 program/e rase cycles, 25 c, typical supply voltage. 3. the maximum program and erase times occu r after the specified number of program /erase cycles. these maximum values are characterized but not guaranteed. 4. actual hardware programming times. this does not include software overhead. table 27. program and erase specifications (code flash) symbol c parameter value unit min typ (1) initial max (2) max (3) table 28. program and erase specifications (data flash) symbol c parameter value unit min typ (1) initial max (2) max (3) t swprogram cc c single word (32 bits) program time (4) ? 30 70 300 s t 16kpperase cc c 16 kb block preprogram and erase time ? 700 800 1500 ms t bank_d cc c 64 kb block preprogram and erase time ? 1900 2300 4800 ms 1. typical program and erase ti mes assume nominal supply values and operati on at 25 c. all times are subject to change pending device characterization. 2. initial factory condition: < 100 program/e rase cycles, 25 c, typical supply voltage. 3. the maximum program and erase times occu r after the specified number of program /erase cycles. these maximum values are characterized but not guaranteed. 4. actual hardware programming times. this does not include software overhead. table 29. flash module life symbol c parameter conditions value unit min typ max p/e cc c number of program/erase cycles per block over the operating temperature range (t j ) 16 kb blocks 100000 ? ? cycles 32 kb blocks 10000 100000 ? cycles 128 kb blocks 1000 100000 ? cycles retention cc c minimum data retention at 85 c average ambient temperature (1) blocks with 0?1000 p/e cycles 20 ? ? years blocks with 1001?10000 p/e cycles 10 ? ? blocks with 10001?100000 p/e cycles 5?? 1. ambient temperature averaged over application duration. it is recommended not to exceed the product operating temperature range. spc560d30x, spc56040dx electrical characteristics doc id 16315 rev 7 51/90 ecc circuitry provides correction of single bit faults and is used to improve further automotive reliability results. some units will experience singl e bit corrections throughout the life of the product with no impact to product reliability. 4.11.2 flash power supply dc characteristics ta bl e 3 1 shows the power supply dc characteristics on external supply. note: power supply for data flash is actually prov ided by code flash; this means that data flash cannot work if code flash is not powered. 4.11.3 start-up/switch-off timings table 30. flash memory read access timing symbol c parameter conditions (1) max unit f cfread cc p maximum working frequency for reading code flash memory at given number of wait states in worst conditions 2 wait states 48 mhz c 0 wait states 20 f dfread cc p maximum working frequency for reading data flash memory at given number of wait states in worst conditions 6 wait states 48 mhz 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified table 31. flash power supply dc electrical characteristics symbol c parameter conditions (1) value unit min typ max i cfread cc d sum of the current consumption on v ddhv and v ddbv on read access flash module read f cpu = 48 mhz code flash ? ? 33 ma i dfread cc d data flash ? ? 4 ma i cfmod cc d sum of the current consumption on v ddhv and v ddbv on matrix modification (program/erase) program/erase on-going while reading flash registers, f cpu = 48 mhz code flash ? ? 33 ma i dfmod cc d data flash ? ? 6 ma i flpw cc d sum of the current consumption on v ddhv and v ddbv during flash low-power mode ? code flash ? ? 910 a i cfpwd cc d sum of the current consumption on v ddhv and v ddbv during flash power-down mode ? code flash ? ? 125 a i dfpwd cc d data flash ? ? 25 a 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified table 32. start-up time/switch-off time symbol c parameter conditions (1) value unit min typ max t flarstexit c c t delay for flash module to exit reset mode code flash ? ? 125 s data flash ? ? 150 s electrical characteristics spc560d30x, spc56040dx 52/90 doc id 16315 rev 7 4.12 electromagnetic compatibility (emc) characteristics susceptibility tests ar e performed on a sample basis du ring product characterization. 4.12.1 designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user apply emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations ?? the software flowchart must include the management of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials ?? most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see the application note software techniques for improving microcontroller emc performance (an1015)). 4.12.2 electromagnetic interference (emi) the product is monitored in terms of emission ba sed on a typical application. this emission test conforms to the iec 61967-1 standard, which specifies the general conditions for emi measurements. t flalpexit c c t delay for flash module to exit low-power mode (2) code flash ? ? 0.5 s t flapdexit c c t delay for flash module to exit power-down mode code flash ? ? 30 s data flash ? ? 30 (3) s t flalpentry c c t delay for flash module to enter low-power mode code flash ? ? 0.5 s t flapdentry c c t delay for flash module to enter power- down mode code flash ? ? 1.5 s data flash ? ? 4 (3) s 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2. data flash does not support low-power mode 3. if code flash is already switched-on. table 32. start-up time/switch-off time (continued) symbol c parameter conditions (1) value unit min typ max spc560d30x, spc56040dx electrical characteristics doc id 16315 rev 7 53/90 4.12.3 absolute maximum rati ngs (electrical sensitivity) based on two different tests (esd and lu) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts (n + 1) supply pin). this test conforms to the aec-q100-002/-003/-011 standard. for more details, refer to the application note electrostatic discharge sensitivity measurement (an1181). table 33. emi radiated emission measurement (1)(2) symbol c parameter conditions value unit min typ max ? sr ? scan range ? 0.150 ? 1000 mhz f cpu sr ? operating frequency ? ? 48 ? mhz v dd_lv sr ? lv operating voltages ? ? 1.28 ? v s emi cc t peak level v dd = 5v, t a =25c, lqfp100 package test conforming to iec 61967-2, f osc = 8 mhz/f cpu = 48 mhz no pll frequency modulation ? ? 18 dbv 2% pll frequency modulation ? ? 14 dbv 1. emi testing and i/o port waveforms per iec 61967-1, -2, -4 2. for information on conducted emission and susceptibility measur ement (norm iec 61967-4), pl ease contact your local marketing representative. table 34. esd absolute maximum ratings (1) (2) symbol c ratings conditions class max value unit v esd(hbm) c c t electrostatic discharge voltage (human body model) t a = 25 c conforming to aec-q100-002 h1c 2000 v v esd(mm) c c t electrostatic discharge voltage (machine model) t a = 25 c conforming to aec-q100-003 m2 200 v v esd(cdm) c c t electrostatic discharge voltage (charged device model) t a = 25 c conforming to aec-q100-011 c3a 500 v 750 (corners) v 1. all esd testing is in conformity with cdf-aec-q100 stress test qualification for automotive grade integrated circuits. 2. a device will be defined as a failure if after exposure to esd pulses the devic e no longer meets the device specification requirements. complete dc parametric and functional testing shall be performed per applicabl e device specification at room temperature followed by hot temperature, unles s specified otherwise in the device specification. electrical characteristics spc560d30x, spc56040dx 54/90 doc id 16315 rev 7 static latch-up (lu) two complementary static tests are required on six parts to assess the latch-up performance: a supply overvoltage is applied to each power supply pin. a current injection is applied to each input, output and configurable i/o pin. these tests are compliant with the eia/jesd 78 ic latch-up standard. table 35. latch-up results symbol c parameter conditions class lu cc t static latch-up class t a = 125 c conforming to jesd 78 ii level a spc560d30x, spc56040dx electrical characteristics doc id 16315 rev 7 55/90 4.13 fast external crystal oscilla tor (4 to 16 mhz) electrical characteristics the device provides an os cillator/resonator driver. figure 9 describes a simple model of the internal oscillator driver and provides an example of a conn ection for an oscillator or a resonator. ta bl e 3 6 provides the parameter description of 4 mhz to 16 mhz crystals used for the design simulations. figure 9. crystal oscillator and resonator connection scheme c2 c1 crystal xtal extal resonator xtal extal device device device xtal extal i r v dd 2. a series resistor may be required, according to crystal oscillator supplier recommendations. 1. xtal/extal must not be directly used to drive external circuits notes: electrical characteristics spc560d30x, spc56040dx 56/90 doc id 16315 rev 7 figure 10. fast external crystal oscillator (4 to 16 mhz) timing diagram table 36. crystal description nominal frequency (mhz) ndk crystal reference crystal equivalent series resistance (esr) ? crystal motional capacitance (c m ) ff crystal motional inductance (l m ) mh load on xtalin/xtalout c 1 =c 2 (pf) (1) shunt capacitance between xtalout and xtalin c0 (2) (pf) 4 nx8045gb 300 2.68 591.0 21 2.93 8 nx5032ga 300 2.46 160.7 17 3.01 10 150 2.93 86.6 15 2.91 12 120 3.11 56.5 15 2.93 16 120 3.90 25.3 10 3.00 1. the values specified for c1 and c2 are the same as used in simulations. it should be ensured that the testing includes all the parasitics (from the board, probe, crystal, et c.) as the ac / transient behavior depends upon them. 2. the value of c0 specified here includes 2 pf additional capacitance for parasitics (to be seen with bond-pads, package, etc.). v fxoscop t fxoscsu v xtal v fxosc valid internal clock 90% 10% 1/f fxosc s_mtrans bit (me_gs register) ?1? ?0? table 37. fast external crystal oscillator (4 to 16 mhz) electrical characteristics symbol c parameter conditions (1) value unit min typ max f fxosc sr ? fast external crystal oscillator frequency ?4.0?16.0mhz spc560d30x, spc56040dx electrical characteristics doc id 16315 rev 7 57/90 g mfxosc cc c fast external crystal oscillator transconductance v dd = 3.3 v 10%, pad3v5v = 1 oscillator_margin = 0 2.2 ? 8.2 ma/v cc p v dd = 5.0 v 10%, pad3v5v = 0 oscillator_margin = 0 2.0 ? 7.4 cc c v dd = 3.3 v 10%, pad3v5v = 1 oscillator_margin = 1 2.7 ? 9.7 cc c v dd = 5.0 v 10%, pad3v5v = 0 oscillator_margin = 1 2.5 ? 9.2 v fxosc cc t oscillation amplitude at extal f osc = 4 mhz, oscillator_margin = 0 1.3 ? ? v f osc = 16 mhz, oscillator_margin = 1 1.3 ? ? v fxoscop cc p oscillation operating point ? ? 0.95 v i fxosc (2) cc t fast external crystal oscillator consumption ??23ma t fxoscsu cc t fast external crystal oscillator start-up time f osc = 4 mhz, oscillator_margin = 0 ?? 6 ms f osc = 16 mhz, oscillator_margin = 1 ??1.8 v ih sr p input high level cmos (schmitt trigger) oscillator bypass mode 0.65v dd ?v dd +0.4 v v il sr p input low level cmos (schmitt trigger) oscillator bypass mode ? 0.4 ? 0.35v dd v 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2. stated values take into account only analog module consum ption but not the digital cont ributor (clock tree and enabled peripherals) table 37. fast external crystal oscillator (4 to 16 mhz) electrical characteristics (continued) symbol c parameter conditions (1) value unit min typ max electrical characteristics spc560d30x, spc56040dx 58/90 doc id 16315 rev 7 4.14 fmpll electrical characteristics the device provides a frequency-modulated phase-locked loop (fmpll) module to generate a fast system clock fr om the main oscillator driver. 4.15 fast internal rc oscillator (16 mhz) electrical characteristics the device provides a 16 mhz fast internal rc oscillator (firc). this is used as the default clock at the power-up of the device. table 38. fmpll electrical characteristics symbol c parameter conditions (1) value unit min typ max f pllin sr ? fmpll reference clock (2) ?4?48mhz ? pllin sr ? fmpll reference clock duty cycle (2) ?40?60% f pllout cc d fmpll output clock frequency ? 16 ? 48 mhz f vco (3) cc p vco frequency without frequency modulation ?256?512 mhz vco frequency with frequency modulation ?245?533 f cpu sr ? system clock frequency ? ? ? 48 mhz f free cc p free-running frequency ? 20 ? 150 mhz t lock cc p fmpll lock time stable oscillator (f pllin = 16 mhz) ? 40 100 s ? t lt j i t cc ? fmpll long term jitter f pllin = 16 mhz (resonator) , f pllclk at 48 mhz, 4000 cycles ? ? 10 ns i pll cc c fmpll consumption t a = 25 c ? ? 4 ma 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2. pllin clock retrieved directly from fxos c clock. input characteristics are granted when oscillator is used in functional mode. when bypass mode is used, os cillator input clock should verify f pllin and ? pllin . 3. frequency modulation is considered 4%. table 39. fast internal rc oscillator (16 mhz) electrical characteristics symbol c parameter conditions (1) value unit min typ max f firc cc p fast internal rc oscillator high frequency t a = 25 c, trimmed ? 16 ? mhz sr ? ? 12 20 i fircrun (2) cc t fast internal rc oscillator high frequency current in running mode t a = 25 c, trimmed ? ? 200 a spc560d30x, spc56040dx electrical characteristics doc id 16315 rev 7 59/90 4.16 slow internal rc oscilla tor (128 khz) electrical characteristics the device provides a 128 khz slow internal rc oscillator (sirc). this can be used as the reference clock for the rtc module. i fircpwd cc d fast internal rc oscillator high frequency current in power down mode t a = 25 c ? ? 10 a i fircstop cc t fast internal rc oscillator high frequency and system clock current in stop mode t a = 25 c sysclk = off ? 500 ? a sysclk = 2 mhz ? 600 ? sysclk = 4 mhz ? 700 ? sysclk = 8 mhz ? 900 ? sysclk = 16 mhz ? 1250 ? t fircsu cc c fast internal rc oscillator start- up time v dd = 5.0 v 10% ? 1.1 2.0 s ? fircpre cc c fast internal rc oscillator precision after software trimming of f firc t a = 25 c ? 1? 1% ? firctrim cc c fast internal rc oscillator trimming step t a = 25 c ? 1.6 % ? fircvar cc c fast internal rc oscillator variation in temperature and supply with respect to f firc at t a = 55 c in high-frequency configuration ? ? 5? 5% 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2. this does not include consumpt ion linked to clock tree toggling and peripher als consumption when rc oscillator is on. table 39. fast internal rc oscillator (16 mhz) electrical characteristics (continued) symbol c parameter conditions (1) value unit min typ max table 40. slow internal rc oscillator (128 khz) electrical characteristics symbol c parameter conditions (1) value unit min typ max f sirc cc p slow internal rc oscillator low frequency t a = 25 c, trimmed ? 128 ? khz sr ? ? 100 ? 150 i sirc (2) cc c slow internal rc oscillator low frequency current t a = 25 c, trimmed ? ? 5 a t sircsu cc p slow internal rc oscillator start-up time t a = 25 c, v dd = 5.0 v 10% ? 8 12 s electrical characteristics spc560d30x, spc56040dx 60/90 doc id 16315 rev 7 ? sircpre cc c slow internal rc oscillator precision after software trimming of f sirc t a = 25 c ? 2? 2 % ? sirctrim cc c slow internal rc oscillator trimming step ??2.7? ? sircvar cc p slow internal rc oscillator variation in temperature and supply with respect to f sirc at t a = 55 c in high frequency configuration high frequency configuration ? 10 ? 10 % 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2. this does not include consumpt ion linked to clock tree toggling and peripher als consumption when rc oscillator is on. table 40. slow internal rc oscillator (128 khz) electrical characteristics (continued) symbol c parameter conditions (1) value unit min typ max spc560d30x, spc56040dx electrical characteristics doc id 16315 rev 7 61/90 4.17 adc electrical characteristics 4.17.1 introduction the device provides a 12-bit successive approximation register (sar) analog-to-digital converter. figure 11. adc characterist ics and error definitions (2) (1) (3) (4) (5) offset error (e o ) offset error (e o ) gain error (e g ) 1 lsb (ideal) 1023 1022 1021 1020 1019 1018 5 4 3 2 1 0 7 6 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 (1) example of an actual transfer curve (2) the ideal transfer curve (3) differential non-linearity error (dnl) (4) integral non-linearity error (inl) (5) center of a step of the actual transfer curve 1 lsb ideal = v dd_adc / 1024 v in(a) (lsb ideal ) code out electrical characteristics spc560d30x, spc56040dx 62/90 doc id 16315 rev 7 4.17.2 input imped ance and adc accuracy in the following analysis, the input circuit corresponding to the precise channels is considered. to preserve the accuracy of the a/d converter, it is necessary that analog input pins have low ac impedance. placing a capacitor with good high frequency characteristics at the input pin of the device can be effective: the capa citor should be as large as possible, ideally infinite. this capacitor contributes to attenuating the noise present on the input pin; furthermore, it sources charge during the sampli ng phase, when the analog signal source is a high-impedance source. a real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple rc filter). the rc filtering may be limited acco rding to the value of source impedance of the transducer or circuit supplying the analog signal to be measured. the filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the adc itself. in fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: being c s and c p2 substantially two switched capacitances, with a frequency equal to the conversion rate of the adc, it can be seen as a resistive path to ground. for instance, assuming a conversion rate of 1 mhz, with c s +c p2 equal to 3 pf, a resistance of 330 k ? is obtained (r eq = 1 / (f c (c s +c p2 )), where f c represents the conversion rate at the considered channel). to minimize the error induced by the voltage partitioning between this resistance (sampled voltage on c s +c p2 ) and the sum of r s + r f , the external circuit must be designed to respect the equation 4 : equation 4 equation 4 generates a constraint for external network design, in particular on a resistive path. v a r s r f + r eq --------------------- ? 1 2 -- -lsb ? spc560d30x, spc56040dx electrical characteristics doc id 16315 rev 7 63/90 figure 12. input equivalent circuit (precise channels) r f c f r s r l r sw1 c p2 c s v dd sampling source filter current limiter external circuit internal circuit scheme c p1 r ad channel selection v a r s : source impedance r f : filter resistance c f : filter capacitance r l : current limiter resistance r sw1 : channel selection switch impedance r ad : sampling switch impedance c p : pin capacitance (two contributions, c p1 and c p2 ) c s : sampling capacitance electrical characteristics spc560d30x, spc56040dx 64/90 doc id 16315 rev 7 figure 13. input equivalent circuit (extended channels) a second aspect involving the capacitance network shall be considered. assuming the three capacitances c f , c p1 and c p2 are initially charged at the source voltage v a (refer to the equivalent circuit in figure 13 ): a charge sharing phenomenon is installed when the sampling phase is started (a/d switch close). figure 14. transient behavior during sampling phase r f c f r s r l r sw1 c p3 c s v dd sampling source filter current limiter external circuit internal circuit scheme c p1 r ad channel selection v a c p2 extended r sw2 switch r s : source impedance r f : filter resistance c f : filter capacitance r l : current limiter resistance r sw1 : channel selection switch impedance (two contributions, r sw1 and r sw2 ) r ad : sampling switch impedance c p : pin capacitance (two contributions, c p1 , c p2 and c p3 ) c s : sampling capacitance v a v a1 v a2 t t s v cs voltage transient on c s ? v < ? 0.5 lsb ? 1 2 ? 1 < (r sw + r ad ) c s << t s ? 2 = r l (c s + c p1 + c p2 ) spc560d30x, spc56040dx electrical characteristics doc id 16315 rev 7 65/90 in particular two different transient periods can be distinguished: 1. a first and quick charge transfer from the internal capacitance c p1 and c p2 to the sampling capacitance c s occurs (c s is supposed initially completely discharged): considering a worst case (since the time cons tant in reality would be faster) in which c p2 is reported in parallel to c p1 (call c p = c p1 + c p2 ), the two capacitances c p and c s are in series, and the time constant is equation 5 equation 5 can again be simplified considering only c s as an additional worst condition. in reality, the transient is faster, but the a/d converter circuitry has been designed to be robust also in the very worst case: the sampling time t s is always much longer than the internal time constant: equation 6 the charge of c p1 and c p2 is redistributed also on c s , determining a new value of the voltage v a1 on the capacitance according to equation 7 : equation 7 2. a second charge transfer involves also c f (that is typically bigger than the on-chip capacitance) through the resistance r l : again considering the worst case in which c p2 and c s were in parallel to c p1 (since the time constant in reality would be faster), the time constant is: equation 8 in this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time t s , a constraints on r l sizing is obtained: equation 9 of course, r l shall be sized also according to the current limitation constraints, in combination with r s (source impedance) and r f (filter resistance). being c f definitively bigger than c p1 , c p2 and c s , then the final voltage v a2 (at the end of the charge transfer transient) will be much higher than v a1 . equation 10 must be respected (charge balance assuming now c s already charged at v a1 ): ? 1 r sw r ad + ?? = c p c s ? c p c s + --------------------- - ? ? 1 r sw r ad + ?? ? c s t s ? ? v a1 c s c p1 c p2 ++ ?? ? v a c p1 c p2 + ?? ? = ? 2 r l ? c s c p1 c p2 ++ ?? ? 10 ? 2 ? 10 r l c s c p1 c p2 ++ ?? ? ? = t s ? electrical characteristics spc560d30x, spc56040dx 66/90 doc id 16315 rev 7 equation 10 the two transients above are not influenced by the voltage source that, due to the presence of the r f c f filter, is not able to provide the extra charge to compensate the voltage drop on c s with respect to the ideal source v a ; the time constant r f c f of the filter is very high with respect to the sampling time (t s ). the filter is typically designed to act as anti-aliasing. figure 15. spectral representation of input signal calling f 0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, f f ), according to the nyquist theorem the conversion rate f c must be at least 2f 0 ; it means that the constant time of the filter is greater than or at least equal to twice the conversion period (t c ). again the conversion period t c is longer than the sampling time t s , which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter r f c f is definitively much higher than the sampling time t s , so the charge level on c s cannot be modified by the analog signal source during the time in which the sampling switch is closed. the considerations above lead to impose new c onstraints on the external circuit, to reduce the accuracy error due to the voltage drop on c s ; from the two charge balance equations above, it is simple to derive equation 11 between the ideal and real sampled voltage on c s : equation 11 from this formula, in the worst case (when v a is maximum, that is for instance 5 v), assuming to accept a maximum error of half a count, a constraint is evident on c f value: v a2 c s c p1 c p2 c f +++ ?? ? v a c f ? v a1 +c p1 c p2 +c s + ?? ? = f 0 f analog source bandwidth (v a ) f 0 f sampled signal spectrum (f c = conversion rate) f c f anti-aliasing filter (f f = rc filter pole) f f 2 f 0 < f c (nyquist) f f = f 0 (anti-aliasing filtering condition) t c < 2 r f c f (conversion rate vs. filter pole) noise v a2 v a ----------- - c p1 c p2 +c f + c p1 c p2 +c f c s ++ ------------------------------------------------------- - = spc560d30x, spc56040dx electrical characteristics doc id 16315 rev 7 67/90 equation 12 4.17.3 adc electrical characteristics c f 2048 c s ? ? table 41. adc input leakage current symbol c parameter conditions value unit min typ max i lkg cc c input leakage current t a = ? 40 c no current injection on adjacent pin ?1? na ct a = 25 c ? 1 ? ct a = 105 c ? 8 200 pt a = 125 c ? 45 400 table 42. adc conversion characteristics symbol c parameter conditions (1) value unit min typ max v ss_adc sr ? voltage on vss_hv_adc (adc reference) pin with respect to ground (v ss ) (2) ? ? 0.1 ? 0.1 v v dd_adc sr ? voltage on vdd_hv_adc pin (adc reference) with respect to ground (v ss ) ?v dd ? 0.1 ? v dd +0.1 v v ainx sr ? analog input voltage (3) ?v ss_adc ? 0.1 ? v dd_adc +0.1 v f adc sr ? adc analog frequency v dd =5.0v 3.33 ? 32 + 4% mhz v dd =3.3v 3.33 ? 20 + 4% ? adc_sys sr ? adc clock duty cycle (ipg_clk) adclksel = 1 (4) 45 ?55 % t adc_pu sr ? adc power up delay ? ?? 1.5 s t s cc t sampling time (5) v dd = 3.3 v f adc = 20 mhz, inpsamp = 12 600 ? ? ns f adc = 3.33 mhz, inpsamp = 255 ? ? 76.2 s t sampling time (5) v dd = 5.0 v f adc = 24 mhz, inpsamp = 13 500 ? ? ns f adc = 3.33 mhz, inpsamp = 255 ? ? 76.2 s electrical characteristics spc560d30x, spc56040dx 68/90 doc id 16315 rev 7 t c cc p conversion time (6) v dd = 3.3 v f adc = 20 mhz, inpcmp = 0 2.4 ? ? s f adc = 13.33 mhz, inpcmp = 0 ??3.6 p conversion time (6) v dd = 5.0 v f adc = 32 mhz, inpcmp = 0 1.5 ? ? s f adc = 13.33 mhz, inpcmp = 0 ??3.6 c s cc d adc input sampling capacitance ? 5 pf c p1 cc d adc input pin capacitance 1 ? 3 pf c p2 cc d adc input pin capacitance 2 ? 1 pf c p3 cc d adc input pin capacitance 3 ? 1.5 pf r sw1 cc d internal resistance of analog source ??? 1 k ? r sw2 cc d internal resistance of analog source ??? 2 k ? r ad cc d internal resistance of analog source ??? 0.3 k ? i inj sr ? input current injection current injection on one adc input, different from the converted one v dd = 3.3 v 10% ? 5? 5 ma v dd = 5.0 v 10% ? 5 ? 5 inlp cc t absolute integral non- linearity-precise channels no overload ?1 3 lsb inlx cc t absolute integral non- linearity-extended channels no overload ?1.5 5 lsb dnl cc t absolute differential non-linearity no overload ?0.5 1 lsb e o cc t absolute offset error ? ?2 ? lsb e g cc t absolute gain error ? ?2 ? lsb tuep (7) cc p total unadjusted error for precise channels, input only pins without current injection ?6 6 lsb t with current injection ?8 8 table 42. adc conversion characteristics (continued) symbol c parameter conditions (1) value unit min typ max spc560d30x, spc56040dx electrical characteristics doc id 16315 rev 7 69/90 4.18 on-chip peripherals 4.18.1 current consumption tuex (7) cc t total unadjusted error for extended channel without current injection ?10 10 lsb t with current injection ?12 12 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2. analog and digital v ss must be common (to be tied together externally). 3. v ainx may exceed v ss_adc and v dd_adc limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped respective ly to 0x000 or 0xfff. 4. duty cycle is ensured by using system clock without prescaling. when adclksel = 0, the duty cycle is ensured by internal divider by 2. 5. during the sampling time the input capacitance c s can be charged/discharged by the ex ternal source. the internal resistance of the analog source must allow the capa citance to reach its final voltage level within t s . after the end of the sampling time t s , changes of the analog input voltage have no effect on the conversion result. values for the sample clock t s depend on programming. 6. this parameter does not include the sampling time t s , but only the time for determining t he digital result and the time to load the result?s register wi th the conversion result. 7. total unadjusted error: the maximum error that occurs wi thout adjusting offset and ga in errors. this error is a combination of offset, gain and integral linearity errors. table 42. adc conversion characteristics (continued) symbol c parameter conditions (1) value unit min typ max table 43. on-chip peripherals current consumption (1) symbol c parameter conditions typical value (2) unit i dd_bv(can) cc t can (flexcan) supply current on v dd_bv 500 kbyte/s total (static + dynamic) consumption: ? flexcan in loop-back mode ? xtal at 8 mhz used as can engine clock source ? message sending period is 580 s 8f periph + 85 a 125 kbyte/s 8 f periph + 27 a i dd_bv(emios) cc t emios supply current on v dd_bv static consumption: ? emios channel off ? global prescaler enabled 29 f periph a dynamic consumption: ? it does not change varying the frequency (0.003 ma) 3a i dd_bv(sci) cc t sci (linflex) supply current on v dd_bv total (static + dynamic) consumption: ?lin mode ? baudrate: 20 kbyte/s 5f periph + 31 a electrical characteristics spc560d30x, spc56040dx 70/90 doc id 16315 rev 7 4.18.2 dspi characteristics i dd_bv(spi) cc t spi (dspi) supply current on v dd_bv ballast static consumption (only clocked) 1 a ballast dynamic consumption (continuous communication): ? baudrate: 2 mbit/s ? transmission every 8 s ? frame: 16 bits 16 f periph a i dd_bv(adc) cc t adc supply current on v dd_bv v dd = 5.5 v ballast static consumption (no conversion) 41 f periph a ballast dynamic consumption (continuous conversion) (3) 5f periph a i dd_hv_adc(adc) cc t adc supply current on v dd_hv_adc v dd = 5.5 v analog static consumption (no conversion) 2f periph a analog dynamic consumption (continuous conversion) 75 f periph + 32 a i dd_hv(flash) cc t cflash + dflash supply current on v dd_hv v dd = 5.5 v ? 8.21 ma i dd_hv(pll) cc t pll supply current on v dd_hv v dd = 5.5 v ? 30 f periph a 1. operating conditions: t a = 25 c, f periph = 8 mhz to 48 mhz 2. f periph is an absolute value. 3. during the conversion, the total current consumption is given from the sum of the static and dynamic consumption, i.e., (41 + 5) f periph . table 43. on-chip peripherals current consumption (1) (continued) symbol c parameter conditions typical value (2) unit table 44. dspi characteristics (1) no. symbol c parameter dspi0/dspi1 unit min typ max 1t sck sr d sck cycle time master mode (mtfe = 0) 125 ? ? ns d slave mode (mtfe = 0) 125 ? ? d master mode (mtfe = 1) 83 ? ? d slave mode (mtfe = 1) 83 ? ? ?f dspi sr d dspi digital controller frequency ? ? f cpu mhz spc560d30x, spc56040dx electrical characteristics doc id 16315 rev 7 71/90 ? ? t csc cc d internal delay between pad associated to sck and pad associated to csn in master mode master mode ? ? 130 (2) ns ? ? t asc cc d internal delay between pad associated to sck and pad associated to csn in master mode for csn1 ? 1 master mode ? ? 130 (2) ns 2t cscext (3) sr d cs to sck delay slave mode 32 ? ? ns 3t ascext (4) sr d after sck delay slave mode 1/f dspi + 5 ? ? ns 4t sdc cc d sck duty cycle master mode ? t sck /2 ? ns sr d slave mode t sck /2 ? ? 5t a sr d slave access time ? 1/f dspi +70 ? ? ns 6t di sr d slave sout disable time ? 7 ? ? ns 7t pcsc sr d pcs x to pcss time ? 0 ? ? ns 8t pasc sr d pcss to pcs x time ? 0 ? ? ns 9t sui sr d data setup time for inputs master mode 43 ? ? ns slave mode 5 ? ? 10 t hi sr d data hold time for inputs master mode 0 ? ? ns slave mode 2 (5) ?? 11 t suo (6) cc d data valid after sck edge master mode ? ? 32 ns slave mode ? ? 52 12 t ho (6) cc d data hold time for outputs master mode 0 ? ? ns slave mode 8 ? ? 1. operating conditions: c out = 10 to 50 pf, slew in = 3.5 to 15 ns 2. maximum is reached when csn pad is configured as slow pad while sck pad is configured as medium pad 3. the t csc delay value is configurable thr ough a register. when configuring t csc (using pcssck and cssck fields in dspi_ctarx registers), delay between internal cs and internal sck must be higher than ? t csc to ensure positive t cscext . 4. the t asc delay value is configurable th rough a register. w hen configuring t asc (using pasc and asc fields in dspi_ctarx registers), delay between internal cs and internal sck must be higher than ? t asc to ensure positive t ascext . 5. this delay value corresponds to smpl_pt = 00b which is bit field 9 and 8 of dspi_mcr. 6. sck and sout configured as medium pad table 44. dspi characteristics (1) (continued) no. symbol c parameter dspi0/dspi1 unit min typ max electrical characteristics spc560d30x, spc56040dx 72/90 doc id 16315 rev 7 figure 16. dspi classic spi timing ? master, cpha = 0 data last data first data first data data last data sin sout pcsx sck output 4 9 12 1 11 10 4 sck output (cpol = 0) (cpol = 1) 3 2 note: numbers shown reference ta b l e 4 4 . spc560d30x, spc56040dx electrical characteristics doc id 16315 rev 7 73/90 figure 17. dspi classic spi timing ? master, cpha = 1 figure 18. dspi classic spi timing ? slave, cpha = 0 data last data first data sin sout 12 11 10 last data data first data sck output sck output pcsx 9 (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 4 4 . last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 12 sck input first data last data sck input 2 (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 4 4 . electrical characteristics spc560d30x, spc56040dx 74/90 doc id 16315 rev 7 figure 19. dspi classic spi timing ? slave, cpha = 1 figure 20. dspi modified transfer format timing ? master, cpha = 0 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 4 4 . pcsx 3 1 4 10 4 9 12 11 sck output sck output sin sout first data data last data first data data last data 2 (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 4 4 . spc560d30x, spc56040dx electrical characteristics doc id 16315 rev 7 75/90 figure 21. dspi modified transfer format timing ? master, cpha = 1 figure 22. dspi modified transfer format timing ? slave, cpha = 0 pcsx 10 9 12 11 sck output sck output sin sout first data data last data first data data last data (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 4 4 . last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 sck input first data last data sck input 2 (cpol = 0) (cpol = 1) 12 note: numbers shown reference ta b l e 4 4 . electrical characteristics spc560d30x, spc56040dx 76/90 doc id 16315 rev 7 figure 23. dspi modified transfer format timing ? slave, cpha = 1 figure 24. dspi pcs strobe (pcss ) timing 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 4 4 . pcsx 7 8 pcss note: numbers shown reference ta bl e 4 4 . spc560d30x, spc56040dx electrical characteristics doc id 16315 rev 7 77/90 4.18.3 jtag characteristics figure 25. timing diagram ? jtag boundary scan table 45. jtag characteristics no. symbol c parameter value unit min typ max 1t jcyc cc d tck cycle time 83.33 ? ? ns 2t tdis cc d tdi setup time 15 ? ? ns 3t tdih cc d tdi hold time 5 ? ? ns 4t tmss cc d tms setup time 15 ? ? ns 5t tmsh cc d tms hold time 5 ? ? ns 6t tdov cc d tck low to tdo valid ? ? 49 ns 7t tdoi cc d tck low to tdo invalid 6 ? ? ns input data valid output data valid data inputs data outputs data outputs tck note: numbers shown reference ta bl e 4 5 . 3/5 2/4 7 6 package characteristics spc560d30x, spc56040dx 78/90 doc id 16315 rev 7 5 package characteristics 5.1 ecopack ? in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 5.2 package mechanical data 5.2.1 lqfp100 figure 26. lqfp100 mechanical drawing spc560d30x, spc56040dx package characteristics doc id 16315 rev 7 79/90 table 46. lqfp100 mechanical data symbol mm inches (1) min typ max min typ max a ? ? 1.600 ? ? 0.0630 a1 0.050 ? 0.150 0.0020 ? 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 ? 0.200 0.0035 ? 0.0079 d 15.800 16.000 16.200 0.6220 0.6299 0.6378 d1 13.800 14.000 14.200 0.5433 0.5512 0.5591 d3 ? 12.000 ? ? 0.4724 ? e 15.800 16.000 16.200 0.6220 0.6299 0.6378 e1 13.800 14.000 14.200 0.5433 0.5512 0.5591 e3 ? 12.000 ? ? 0.4724 ? e ? 0.500 ? ? 0.0197 ? l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 ? 1.000 ? ? 0.0394 ? k 0.0 3.5 7.0 0.0 3.5 7.0 tolerance mm inches ccc 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. package characteristics spc560d30x, spc56040dx 80/90 doc id 16315 rev 7 5.2.2 lqfp64 figure 27. lqfp64 mechanical drawing 5w_me l a1 k l1 c a a2 ccc c d d1 d3 e3 e1 e 32 33 48 49 b 64 1 pin 1 identification 16 17 table 47. lqfp64 mechanical data symbol mm inches (1) min typ max min typ max a ? ? 1.6 ? ? 0.0630 a1 0.05 ? 0.15 0.0020 ? 0.0059 a2 1.35 1.4 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 ? 0.2 0.0035 ? 0.0079 d 11.8 12 12.2 0.4646 0.4724 0.4803 d1 9.8 10 10.2 0.3858 0.3937 0.4016 d3 ? 7.5 ? ? 0.2953 ? e 11.8 12 12.2 0.4646 0.4724 0.4803 e1 9.8 10 10.2 0.3858 0.3937 0.4016 e3 ? 7.5 ? ? 0.2953 ? e?0.5??0.0197? l 0.45 0.6 0.75 0.0177 0.0236 0.0295 l1 ? 1 ? ? 0.0394 ? spc560d30x, spc56040dx package characteristics doc id 16315 rev 7 81/90 k 0.03.57.00.03.57.0 ccc ? ? 0.08 ? ? 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 47. lqfp64 mechanical data (continued) symbol mm inches (1) min typ max min typ max ordering information spc560d30x, spc56040dx 82/90 doc id 16315 rev 7 6 ordering information table 48. order codes order code cpu memory package op. temp. (c) speed (mhz) voltag e packing code flash / sram (kb) data flash spc560d30l1b3e0x e200z0h 128 / 12 4 x 16 kb lqfp64 ? 40 to 105 32 3.3 / 5 v tape & reel spc560d30l1c3e0x ? 40 to 125 SPC560D30L1B4E0X e200z0h 128 / 12 4 x 16 kb lqfp64 ? 40 to 105 48 3.3 / 5 v tape & reel spc560d30l1c4e0x ? 40 to 125 spc560d30l1b3e0x e200z0h 128 / 12 4 x 16 kb lqfp64 ? 40 to 105 32 3.3 / 5 v tape & reel spc560d30l1c3e0x ? 40 to 125 SPC560D30L1B4E0X e200z0h 128 / 12 4 x 16 kb lqfp64 ? 40 to 105 48 3.3 / 5 v tape & reel spc560d30l1c4e0x ? 40 to 125 spc560d40l3b3e0x e200z0h 256 / 16 4 x 16 kb lqfp100 ? 40 to 105 32 3.3 / 5 v tape & reel spc560d40l3c3e0x ? 40 to 125 spc560d40l3b4e0x e200z0h 256 / 16 4 x 16 kb lqfp100 ? 40 to 105 48 3.3 / 5 v tape & reel spc560d40l3c4e0x ? 40 to 125 spc560d40l3b3e0x e200z0h 256 / 16 4 x 16 kb lqfp100 ? 40 to 105 32 3.3 / 5 v tape & reel spc560d40l3c3e0x ? 40 to 125 spc560d40l3b4e0x e200z0h 256 / 16 4 x 16 kb lqfp100 ? 40 to 105 48 3.3 / 5 v tape & reel spc560d40l3c4e0x ? 40 to 125 table 49. order codes for engineering samples (1) order code cpu memory package op. temp. (c) speed (mhz) voltag e packing code flash / sram (kb) data flash spc560d40l1-eng e200z0h 256 / 16 4 x 16 kb lqfp64 ? 40 to 125 48 3.3 / 5 v tape & reel spc560d40l3-eng lqfp100 1. engineering samples are suitable only for evaluation and developm ent purpose but not for qual ification and production. their silicon version and matu rity may vary until the pr oduct has reached qualification. spc560d30x, spc56040dx ordering information doc id 16315 rev 7 83/90 figure 28. commercial product code structure memory packing core family y = tray x = tape and reel 90 3e0 = 32 mhz eeprom 5v/3v 4e0 = 48 mhz eeprom 5v/3v b = ?40 to 105 c c = ?40 to 125 c l1 = lqfp64 l3 = lqfp100 40 = 256 kb 30 = 128 kb d = access family 0 = e200z0h spc56 = power architecture in 90 nm temperature package custom version spc56 40 y 0d c l3 4e0 example code: product identifier ordering information spc560d30x, spc56040dx 84/90 doc id 16315 rev 7 appendix a abbreviations ta bl e 5 0 lists abbreviations used in this document. table 50. abbreviations abbreviation meaning apu auxilliary processing unit cmos complementary metal?oxide?semiconductor cpha clock phase cpol clock polarity cs peripheral chip select daoc double action output compare ecc error code correction evto event out gpio general purpose input/output ipm input period measurement ipwm input pulse width measurement mb message buffer mc modulus counter mcb modulus counter buffered (up / down) mcko message clock out mdo message data out mseo message start/end out mtfe modified timing format enable nvusro non-volatile user options register opwfmb output pulse width and frequency modulation buffered opwmb output pulse width modulation buffered opwmcb center aligned output pulse widt h modulation buffered with dead time opwmt output pulse width modulation trigger pwm pulse width modulation saic single action input capture saoc single action output compare sck serial communications clock sout serial data out tbd to be defined tck test clock input tdi test data input spc560d30x, spc56040dx ordering information doc id 16315 rev 7 85/90 tdo test data output tms test mode select table 50. abbreviations (continued) abbreviation meaning revision history spc560d30x, spc560d40x 86/90 doc id 16315 rev 7 revision history ta bl e 5 1 summarizes revisions to this document. table 51. document revision history date revision changes 09-jul-2009 1 initial release. 18-feb-2010 2 updated the following tables: - absolute maximum ratings - low voltage power domain electrical characteristics; - on-chip peripherals current consumption - dspi characteristics; - jtag characteristics; - adc conversion characteristics; inserted a note on ?flash power supply dc characteristics? section. 10-aug-2010 3 ?features? section: updated info rmation concerning emios, adc, linflex, nexus and low power capabilities ?pictus 512k device comparison? table: updated the ?execution speed? row ?pictus 512k series block diagram? figure: ? updated max number of crossbar switches ? updated legend ?pictus 512k series block summary? table: added contents concernig the edma block ?lqfp100 pin configuration (top view)? figure: ? removed alternate functions ? updated supply pins ?lqfp64 pin configuration (top view)? figure: removed alternate functions added ?pin muxing? section ?nvusro register? section: deleted ?nvusro[watchdog_en] field description? section ?recommended operating conditions (3.3 v)? table: ?tv dd : deleted min value ? in footnote no. 3, changed capacitance value between v dd_bv and v ss_lv ?recommended operating conditions (5.0 v)? table: deleted tv dd min value ?lqfp thermal characteristics? table: changed r ? jc values ?i/o input dc electrical characteristics? table: ?w fi : updated max value ?w nfi : updated min value ?i/o consumption? table: removed i dynseg row added ?i/o weight? table ?program and erase specifications (code flash)? table: deleted t bank_c row spc560d30x, spc560d40x revision history doc id 16315 rev 7 87/90 10-aug-2010 3 (cont.) updated the following tables: ? ?voltage regulator electrical characteristics? ? ?low voltage monitor electrical characteristics? ? ?low voltage power domain electrical characteristics? ? ?start-up time/switch-off time? ? ?fast external crystal oscillator (4 to 16 mhz) electrical characteristics? ? ?fmpll electrical characteristics? ? ?fast internal rc oscillator (16 mhz) electrical characteristics? ? ?adc conversion characteristics? ? ?on-chip peripherals current consumption? ? ?dspi characteristics? ?dspi characteristics? section: removed ?dspi pcs strobe (pcss) timing? figure updated ?order codes? table added ?order codes for engineering samples? table updated ?commercial product code structure? table 16-sep-2011 4 formatting and editorial changes throughout device comparison table: for the ?total timer i/o emios?, changed ?13 ch? to ?14 ch? spc560d30/spc560d40 series block summary: ? added definition for ?autosar? acronym ? changed ?system watchdog timer? to ?software watchdog timer? lqfp64 pin configuration (top vi ew): changed pin 6 from vpp_test to vss_hv added section ?pad configuration during reset phases? added section ?voltage supply pins? added section ?pad types? added section ?system pins? renamed and updated section ?functional ports? (was previously section ?pin muxing?); update includes replacing all instances of wkup with wkpu (wkpu is the correct abbreviation for wakeup unit) section ?nvusro register?: edited co ntent to separate configuration into electrical parameters and digital functionality added section ?nvusro[watchdog_en] field description? absolute maximum ratings: re moved ?c? column from table replaced ?tbd? with ??? in t vdd min value cell of 3.3 v and 5 v recommended operating conditions tables lqfp thermal characteristics: removed r ? jb single layer board conditions; updated footnote 4 i/o input dc electrical characteristics: removed footnote ?all values need to be confirmed during device validation?; updated i lkg characteristics table 51. document revision history (continued) date revision changes revision history spc560d30x, spc560d40x 88/90 doc id 16315 rev 7 16-sep-2011 4 (cont.) medium configuration output buffer electrical characteristics: changed ?i oh = 100 a? to ?i ol = 100 a? in v ol conditions i/o consumption: replaced instan ces of ?root medium square? with ?root mean square? updated section ?voltage regulator electrical characteristics? section ?low voltage detector elec trical characteristics?: changed title (was ?voltage monitor electrical characteristics?); added a fifth lvd (lvdhv3b); added event status flag names found in rgm chapter of device reference manual to por module and lvd descriptions; replaced instances of ?low voltage monitor? with ?low voltage detector?; deleted note referencing power domain no. 2 (this domain is not present on the device); updated electrical characteristics table updated and renamed section ?power consumption? (was previously section ?low voltage domain power consumption?) program and erase specifications (code flash): updated symbols; updated t esus values updated flash memory read access timing emi radiated emission measurement: updated s emi values updated fmpll electrical characteristics crystal oscillator and resonator connection scheme: inserted footnote about possibly requiring a series resistor fast internal rc oscillator (16 mh z) electrical characteristics: updated t fircsu values section ?input impedance and adc accuracy?: changed ?v a /v a2 ? to ?v a2 /v a ? in equation 13 adc conversion characteristics: ? updated conditions for sampling time v dd = 5.0 v ? updated conditions for conversion time v dd =5.0 v updated abbreviations removed order codes tables. 01-dec-2011 5 replaced ?tbd? with ?8.21 ma? in i dd_hv(flash) cell of on-chip peripherals current consumption table table 51. document revision history (continued) date revision changes spc560d30x, spc560d40x revision history doc id 16315 rev 7 89/90 04-feb-2013 6 removed all instances of table footnote ?all values need to be confirmed during device validation? section 4.1, introduction , removed caution note. table 11 (recommended operating conditions (3.3 v)) , added minimum value of t vdd and footnote about it. table 12 (recommended operating conditions (5.0 v)) , added minimum value of t vdd and footnote about it. updated section 4.17.2, input impedance and adc accuracy in ta b l e 2 4 , changed v lv d h v 3 l , v lvdhv3bl from 2.7 v to 2.6 v. revised the table 28 (flash module life) updated table 43, dspi characteristics , to add specifications 7 and 8, t pcsc and t pasc . inserted figure 24 , dspi pcs strobe (pcss) timing. 17-sep-2013 7 updated disclaimer. table 51. document revision history (continued) date revision changes spc560d30x, spc56040dx 90/90 doc id 16315 rev 7 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particul ar purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ? 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